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Interfacing Processors and Peripherals

I. n. t. e. r. r. u. p. t. s. P. r. o. c. e. s. s. o. r. C. a. c. h. e. M. e. m. o. r. y. –. I. /. O. b. u. s. I. /. O. I. /. O. I. /. O. c. o. n. t. r. o. l. l. e. r. c. o. n. t. r. o. l. l. e. r. c. o. n. t. r. o. l. l. e.

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Interfacing Processors and Peripherals

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  1. I n t e r r u p t s P r o c e s s o r C a c h e M e m o r y – I / O b u s I / O I / O I / O c o n t r o l l e r c o n t r o l l e r c o n t r o l l e r M a i n m e m o r y N e t w o r k G r a p h i c s D i s k D i s k o u t p u t Interfacing Processors and Peripherals

  2. I/O Devices

  3. Input/Output • Very diverse devices • behaviour (i.e., input vs. output) • partner (who is at the other end?) • data rate • Important but neglected • difficulties in assessing and designing I/O systems have often relegated I/O to second class status

  4. Input/Output • I/O design affected by performance, expandability, resilience, etc. • I/O System performance depends on: • CPU • memory system (caches, main memory) • buses • I/O controller • I/O device • I/O software (operating system) • Performance metrics: • throughput: I/O bandwidth • response time: latency

  5. P l a t t e r s T r a c k s P l a t t e r S e c t o r s T r a c k I/O Example: Disk Drives To access data: — seek: position head over the proper track ( 6 ms) — rotational latency: wait for desired sector ( 4 ms) — transfer: one or more sectors ( 15 MB/s)

  6. Buses • Shared communication link (one or more wires) • Types of buses: • processor–memory (short, high speed, custom design) • backplane (high speed, often standardised, e.g., PCI) • I/O (lengthy, different devices, standardised, e.g., SCSI) • Synchronous • use a clock and a synchronous protocol, fast and small • every device must operate at same rate • wait states possible • clock skew requires the bus to be short • Asynchronous • doesn’t use a clock • uses handshaking

  7. Bus Design • Difficult • may be a bottleneck • length of the bus • number of devices • tradeoffs (buffers for higher bandwidth increase latency) • support for many different devices • cost

  8. B a c k p l a n e b u s P r o c e s s o r M e m o r y a . I / O d e v i c e s P r o c e s s o r - m e m o r y b u s P r o c e s s o r M e m o r y B u s B u s B u s a d a p t e r a d a p t e r a d a p t e r I / O I / O I / O b u s b u s b u s b . Bus Structures

  9. P r o c e s s o r - m e m o r y b u s P r o c e s s o r M e m o r y B u s a d a p t e r I / O b u s B u s a d a p t e r B a c k p l a n e b u s I / O b u s B u s a d a p t e r c . Bus Structures

  10. T1 T2 T3 Clock Address lines Memory address From processor AS R/W Bi- directional Data lines Data from memory Data accepted by processor Synchronous Bus Transfer Example: Read

  11. T1 T2 T3 Clock Address lines Memory address From processor AS R/W Bi- directional Data lines Data from processor Synchronous Bus Transfer Example: Write

  12. T1 T2 Tw T3 Clock Address lines Memory address From processor AS R/W From memory WAIT Bi- directional Data lines Data from processor WAIT checked by processor Synchronous Write with a Wait State

  13. Asynchronous Handshaking Example • A device requests a word from the memory • Three control lines • ReadReq: indicates a read request for memory • DataRdy: indicates the word is ready on the data lines • Ack: acknowledges the Req or Rdy signal of the other party

  14. R e a d R e q 1 3 D a t a 4 2 6 2 4 A c k 5 7 D a t a R d y Asynchronous Handshaking Waveforms address data

  15. Controlling Bus Access • A bus master controls access to the bus • it initiates and controls all bus requests • the slave responds to requests • Single bus master • the processor • Multiple bus masters • bus arbitration

  16. Bus Arbitration • daisy chain arbitration • bus granted in priority order • a grant line runs through the devices • centralized, parallel arbitration • centralised arbiter chooses from among requesting devices • e.g., PCI • distributed arbitration by self-selection • each requesting device makes a request on the bus and determines independently who has the highest priority • e.g., NuBus used in Macintosh • distributed arbitration by collision detection • each device independently requests the bus, collisions are detected • e.g., Ethernet

  17. Operating system • Responsibilities of the OS arise from • I/O system is shared by multiple programs • I/O systems often use interrupts • low-level control of an I/O device is complex: concurrent events, detailed requirements • Functions the OS must provide • protection, by maintaining user rights • abstractions for accessing devices • interrupt handling • equitable access to shared I/O resources • Three types of communication • OS gives commands to the devices • devices notify the OS when operations are completed • data transfer between memory and an I/O device

  18. Giving Commands to I/O Devices • Special I/O instructions specifying • device number • command word • Memory-mapped I/O • portions of the address space are assigned to I/O devices • those addresses are used by the control, status and data registers of the devices • reads and writes to those addresses are interpreted as commands to the I/O devices • user programs are prevented from issuing I/O operations directly

  19. Communicating with the Processor • The OS needs to know when • the I/O device has completed an operation • the I/O operation has encounted an error • Methods • polling • interrupt-driven I/O • Polling • the I/O devices put information in status registers • the OS periodically checks the status registers • simple: the processor is totally in control and does all the work • consumes a lot of processor time

  20. Communicating with the Processor • Interrupt-driven I/O • I/O interrupts are just like exceptions except: • an I/O interrupt is asynchronous • further information needs to be conveyed • interrupts indicate to the processor that an I/O device needs attention • user program progress is only halted but special hardware is needed to • send a request (device) • detect an interrupt (processor) • save the CPU state during the interrupt service routine (processor)

  21. Direct Memory Access • External to the CPU • Direct transfer of data to or from the memory without involving the processor • The DMA controller becomes the bus master and directs the reads and writes • Steps in a DMA transfer • the processor supplies the identity of the device, the operation, the memory address and the number of bytes • the DMA controller completes the operation without bothering the processor • the DMA controller interrupts the processor to inform that the transfer is complete

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