1 / 14

Preparation of Mock tile MCPs 01042011

Preparation of Mock tile MCPs 01042011. Anil Mane, Qing Peng, Jeffrey Elam Argonne National Laboratory. Objective:. To prepare 8 workable MCPs for mock tile assembly Collect within batch MCPs resistance data for resistive coating ALD process

favian
Download Presentation

Preparation of Mock tile MCPs 01042011

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Preparation of Mock tile MCPs01042011 Anil Mane, Qing Peng, Jeffrey Elam Argonne National Laboratory

  2. Objective: • To prepare 8 workable MCPs for mock tile assembly • Collect within batch MCPs resistance data for resistive coating ALD process • Collect batch-to-batch MCPs resistance data for resistive coating ALD process Experimental: • Used 2 batch of 5 MCPs with NiCr electrode • Passivation (53A) • Resistive coating chemistry-2 (~800A) • SEE coating (53A)

  3. NiCr deposition at Fermi lab: NiCr electrode on 1st batch of 5 MCPs MCP# 125 126 127 128 129 NiCr electrode on 2nd batch of 5 MCPs MCP# 130 131 132 133 134 • One of the MCP holder has electrode exposure dimension issue

  4. MCPs placement prior to ALD in substrate loading tray MCP with NiCr electrode Before ALD MCP# 125 126 127 128 129 After ALD • Uniform deposition on monitors (quartz and Si(100)) as well as on all MCPs

  5. ALD coating thickness across the reactor • Thickness uniformity on monitor Si(100) <2% • The resistive layer thickness ~800A • Similar thickness trend observed on second batch of 5 MCPs •  Excellent batch-to-batch reproducibility

  6. I-V(-10V to +10V) Response in air for 10 MCPs Removed MCP 131 data • Linear I-V response for all MCPs • MCP 131 resistance is out of targeted value (Outlier) • Little scatter in I-V plot

  7. I-V(-100V to +100V) Response in vacuum (4e-3mbar) for 10 MCPs Removed MCP 131 data • Linear I-V response for all MCPs • MCP 131 resistance is out of targeted value • Little scatter in I-V plot

  8. I-V Comparison (air vs. vacuum) 9 MCPs I-V in Vacuum (4e-3mbar) I-V in Air -10V to +10V -100V to +100V • Linear I-V response for all MCPs • Very little change in I-V values • Little scatter in I-V plot • Electrical contact cause by electrode underneath? • Related to end spoiling ? • ALD chemistry composition across the reactor? • Electrode area ?

  9. Resistance Comparison for 9 MCPs (air vs. vacuum) • Very little change in average resistance ( air 111 M vs. vacuum 115 M) • Average resistance in vacuum = 115 ±12 M  ~10% resistance variation

  10. Resistance for 10 MCPs What's wrong with MCP# 131?

  11. Resistance for 10 MCPs • Cause for outlier (MCP131):

  12. Resistance for 10 MCPs • Gap in triple points can cause electrode • penetration and cause localize • low resistance regimes • Will affect greatly on 8”x8” MCP • Need minimum(?) defects on MCPs • Cause for outlier (MCP131):

  13. Summary • Prepared 10 MCPs with ALD resistive layer chemistry-2 and SEE (Al2O3) layer • Excellent resistive layer uniformity across the ALD reactor • Within batch good ALD layer reproducibility • Very good batch-to-batch reproducible of ALD process • All MCPs shows linear I-V response • Very little change in resistance of MCPs (Air vs. Vacuum) • Average resistance for MCP = 115M • Big gap @ triple point are responsible for outliers • NiCr electrode deposition need same dimension MCP holders • Will vary the total # of active pores (resistances)

  14. Next plan for Mock tile: • Selected 8 MCPs Gain test in APS test set-up • George and grid (A, B, & C) spacer resistance tuning • Resistance test on stack of [MCPs, George and & spacer (A, B, & C ) on Mock tile • Gain test at UCB (Prof. Ossy’s Lab)

More Related