In-chip and Inter-chip Interconnections and data transportations for

1. In-chip and Inter-chip Interconnections and data transportations for Future MPAR Digital Receiving System A presentation for LOMC-MPAR project kickoff Dr. Yan Zhang School of Electrical and Computer Engineering University of Oklahoma

2. Analog beamformers Overview of future MPAR architecture From antennas Backplane processors Digital Transceiver Digital Transceiver Digital Transceiver Digital beamformer (function/frequency 1) Digital beamformer (function/frequency N) A mesh network model

3. MPAR data transaction types Source / end Potential requirements ADC to Digital Pre-filter high speed, low-latency, general point-to-point allow small # of packet dropping Digital pre-filter to digital beamformers high speed, low latency, multicast, and more strict (DBF) requirement on packet dropping DBF processing module median speed, low-median latency, point-to-point To DBF processing module median-high transportation reliability, possible on-chip DBF to backplane processors lower speed, higher latency, point to multi-point, highest transportation reliability Control and synchronization signals low speed, low latency messaging, strict timing requirement, high transportation reliability

4. Overall requirements Open architecture (scalability and survivability) Parallel-scheme communication data bandwidth: ~ 10 Gbps Embedded system application Low-latency (e.g., P-to-P < 100 ns) High efficiency Immunity to noise and interference Lowest pin-count and cost

5. Some current backplane and interconnection technologies Shared bus… VME (< 66MHz) Hierarchical bus… PCI (< 133 MHz) PCI Express (< 10 GHz) Packet-switching Gigabit Ethernet (IEEE 802.3z) On-chip Peripheral Bus (OPB) or Processor Local Bus (PLB) (Xilinx and IBM) Inter -connection (lessons learnt…) Chip-to-chip Board-to-board Algorithm-to-algorithm Real-time distributed computing Data-transportation

6. A new interconnection and data transportation technology Point-to-Point Switching Fabric ‘straightforward’ routing Packetized ‘divide data stream into small packets’ Serial differential pairs on PCB ‘low-power, reliable and low-cost’ Simple protocol – no OS requirement ‘different from Ethernet!’ Protocol FSM SERDES Switch fabric Diff pairs Diff pairs SERDES Protocol FSM Embedded transceiver Other switches/ endpoints FIFO management Clock correction Channel bonding 8B/10B codec Clock management

7. Existing High-speed serial IO Standards Speed #of Diff Pairs application area cost and complexity RapidIO 1.25/2/5/3.125 Gbps 1, 4 or 16 lanes DSP farms, processor low and low power (per lane) ASIC and FPGA LVDS 500M-1.5 Gbps 1 telecommunications low and low power computer and high-speed point-to-point link RocketIO 622M-6.25 Gbps up to 24 transceiver Xilinx FPGA, chip and low (per lane) lanes backplane XAUI 3.125/3/75 Gbps 4 backplane, computer high and high power (10 networks consumption Gigabit Ethernet) (Physical layer compatible) RapidIO fits our needs better because it’s scalable-modular, high-speed, robust, simple and lower cost ― Highest effective speed over minimum physical resource

8. Effective Bandwidth comparison Protocol Efficiency comparison (RapidIO, Gigabit-Ethernet and PCI Express)

9. On-chip parallel bus Data acquisition On-chip controller Digital filtering Data acquisition On-chip controller Serial transceiver Digital filtering DBF Serial transceiver DBF Reconfigurable nodes Serial IO Switch chip boundary Serial IO Switch On-chip controller Local memory banks A complete picture of conceptual digital receiving system Serial transceiver

10. Customized serial IO channel for MPAR: Challenges Protocol system • A light-weight protocol stack for MPAR • Avoid using operating system • ‘smart’ routing and survivability • Physical channel design: for improved eye diagram on low-cost PCB • Physical layer techniques (8b/10b codec, pre-emphasis) • minimize BER MPAR application Logic Signal integrity Transport Physical Customized Logic/Application layer • Customized logic functions • Transaction type for PAR • Raw-data transmission and memory addressing

11. Black box of the left specific Differential Pair Differential output with different output capacitances Signal integrity research Differential Pair Models & Simulation results Tools: Ansoft Designer/ HFSS

12. Experimental System Digital Storage Oscilloscope Daughter card slot for ADC and digital receiver Probing system FPGA with protocol Stack and self- monitoring PCB Serial RIO switch (Tundra) Demonstrate the data IO Speed and performance Explore various architectures Evaluate application on MPAR To other endpoints

13. Radar applications: Current progress of other groups University of Florida Build a 4-node FPGA RIO testbed with switch, also simulation (2006) environment with MLDesigner -- for space-based radar and real-time GMTI Drexel University Build a RapidIO simulator for 8-node parallel RIO network (2001, sponsored by Navy) Mercury (2006) Using RapidIO in one of the Ehotek digital receiver products Computer systems LVDS (non-networking) applications are mainly about video data link, LCD and ADC

14. OU’s team work Development team Dr Yan Zhang: High-speed system interconnection and MPAR radar Dr Mark Yeary: Digital filtering algorithm, DSP and software-defined radio Mr. XXX: graduate student, signal integrity, FPGA, software radio and RapidIO R&D Advisory team Dr. Jerry Crain: Antenna, RF, MPAR system issues Dr. Robert Palmer: Algorithm, Phased array signal processing Mr. Chad Kidder: Technical manager of Radar Innovations Lab

15. Our plan and schedule Month 1 2 3 4 5 6 7 8 9 10 11 12 A B C D • Compare serial IO standards and requirements • Design the costumed IO protocols and processing engine • Experimental Systems including signal integrity solutions • Test and analysis