Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors. Abhishek Bhattacharjee and Margaret Martonosi Department of Electrical Engineering Princeton University ASPLOS’10 . TLB management. Hardware-managed TLB No need for expensive interrupts
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Inter-Core Cooperative TLB Prefetchersfor Chip Multiprocessors
AbhishekBhattacharjee and Margaret Martonosi
Department of Electrical Engineering
exist in TLB miss patterns
among multiple cores.
16 entries in PB, Average 46%