Analysis and Design of RF CMOS Attenuators

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Analysis and Design of RF CMOS Attenuators

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1. Analysis and Design of RF CMOS Attenuators Hakan Dogan, Robert G. Meyer and Ali M. Niknejad Berkeley Wireless Research Center University of California, Berkeley

3. Motivation Motivation: Precise gain control is required for many RF applications at the RF front end or at Intermediate Frequencies. Cable modem tuner, fiber receivers IS-95 CDMA mobile receiver Instrumentation (Testing equipment, function generators, oscilloscopes) Terrestrial Receivers (Satellite Radio) Important Design Parameters Insertion Loss: Minimum achievable attenuation S11 & S22 : Adequate matching to source & load impedances Bandwidth: Maximum achievable bandwidth for a given technology Distortion: IIP2 & IIP3 performance

4. System Example: Cable TV tuner Variable gain element is present in both the up-converter and down-converter Wide band systems require highly linear building blocks High linearity VGAs consume large amounts of power Replacing VGAs with on-chip attenuators will relax the design specs and lower power dissipation

5. Attenuator vs. VGA Any attenuation before the constant gain amplifier will add to its linearity 20-25dBm IIP3 commercial VGAs consume 70-100mA from 3.3V supply High linearity attenuator (25dBm) with a medium linearity (10dBm) amplifier can be achieved with 15-20mA High 1dB compression point of the attenuator will allow larger input swing

6. Attenuator Topologies What limits performance in terms of design parameters e.g. insertion loss, bandwidth, distortion etc. ? How do the two topologies compare in terms of performance? What can we achieve with the latest CMOS technologies? Is linearity the performance bottleneck?

7. Minimum Insertion Loss The loss at the output when a device is inserted in the signal path Shunt devices are off, RS matches to RM+Rl Increasing device sizes for the series transistor decreases the insertion loss Data is generated using ST 0.13Á digital CMOS process with 1.2V supply voltage

8. Maximum Attenuation

9. Impedance Matching

10. Frequency Limitations For high attenuation multiple stage attenuator design is advantageous Conductive substrate will limit max. attenuation at high frequencies Pi or T double stage is sufficient for applications up to 5GHz Design choice will be based on distortion performance by trading off bandwidth with linearity

11. Distortion: Device Equation Collapses to (1) for strong inversion in linear region and to (2) for weak inversion Models the transition region of moderate inversion with acceptable accuracy

12. Distortion Performance (1) Increasing attenuation causes larger swing across the series device Distortion degrades with attenuation Higher attenuation means larger input drive, linearity should improve Simulated at 100MHz and 2.5GHz

13. Distortion degrades as the parallel device starts conducting Series devices matches to 50O at max. attenuation (Vctrl~Vth), limits distortion degradation Worst case distortion is better than the ? configuration Simulated at 100MHz

14. Shunt R forces the series devices to turn off at high attenuation Distortion improves at high attenuation as the series devices completely turn off Simulated at 100MHz

15. Attenuator Block Diagram Dummy attenuator is used in a DC feedback loop for impedance matching Vctrl varies the series resistance for attenuation Feedback amplifier forces shunt device resistance to match to Rs & Rl Same control voltages are applied to RF attenuator

16. Linearity Improvement Un-identical cascaded stages 1st stage is highly linear at 12dB attenuation Limits the signal to the 2nd stage, improving its linearity Asymmetric topology requires separate feedback loop for input and output matching

17. Attenuation Range Vctrl2 is offset from Vctrl1 to achieve a smooth attenuation curve

18. Design Schematic

19. Chip Photo Dimensions: 700x1000 Ám2 Process: 0.13-Ám bulk CMOS from ST Microelectronics Chip was probed for testing.

20. Measurement Results (I)

21. Measurement Results (II)

22. Design Comparison

23. Conclusion CMOS attenuator circuits have been analyzed for attenuation range, frequency and distortion performance Intermodulation distortion equations have been derived using a simple CMOS model An improved distortion attenuator design has been presented The design performance has been verified through testing

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