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Analysis and Design of CMOS Analog Building Blocks

Analysis and Design of CMOS Analog Building Blocks. Márcio Cherem Schneider. Universidade Federal de Santa Catarina. Contents. The intrinsic gain stage The source-coupled pair The two-transistor current mirror A self-biased current source. Summary of main design equations.

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Analysis and Design of CMOS Analog Building Blocks

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  1. Analysis and Design of CMOS Analog Building Blocks Márcio Cherem Schneider UniversidadeFederal de Santa Catarina Analysis and design of CMOS analog building blocks

  2. Contents The intrinsic gain stage The source-coupled pair The two-transistor current mirror A self-biased current source Analysis and design of CMOS analog building blocks

  3. Summary of main design equations Technology parameters Forward and reverse currents Size- and bias-related transistor parameters UICM 0.35 um CMOS technology Saturation voltage Saturation Analysis and design of CMOS analog building blocks

  4. VDD vo vo=vi VDD M2 IB VDSsat2 IL Vmax Av maximum output swing ID M1 CL Vmin + VDSsat1 VI vi VTH VDD vi VDD 0 |AV0|dB 0 ~3 if THE INTRINSIC GAIN STAGE - 1 M1,M2 in saturation Class A amplifier: SR->SR+. From UICM we find the dc voltage VTH at the input: Low-frequency gain versus inversion level Analysis and design of CMOS analog building blocks

  5. |AV|dB VDD |AV0| IB -20 dB/dec IL ID 0 u b  M CL + VI vo vg + vi go CL gmvg is the transconductance is the output impedance THE INTRINSIC GAIN STAGE - 2 V-I converter (transconductor) followed by an I-V converter (output impedance) VO Voltage gain vs frequency Analysis and design of CMOS analog building blocks

  6. VDD IB IL vo ID vg M1 CL + + vi VI go CL gmvg ECF THE INTRINSIC GAIN STAGE - 3 VO Sizing and biasing: W, L, IB Power-area tradeoff How long can L be? CIN and transit time are both proportional to L2 (for constant W/L)! Analysis and design of CMOS analog building blocks

  7. VDD VO Noiseless MOST - + IB IL ID M1 CL + VI 0.35 um CMOS technology 1/2 (WI) 2/3 (SI) THE INTRINSIC GAIN STAGE - 4 Thermal 1/f MOST noise model Bias-dependent factor Corner frequency Noise current generator Input-referred noise model Analysis and design of CMOS analog building blocks

  8. I1 I2 M1 M2 + vG2 - + vG1 - IT VSS 1 <1 10 100 it=1000 I1/IT I2/IT -12 -8 -4 0 4 8 12 THE SOURCE-COUPLED PAIR -1 • First order analysis: • Ideal current source • M1 & M2 in saturation  I1 & I2 independent of drain voltage; Normalization Analysis and design of CMOS analog building blocks

  9. I1 I2 M1 M2 + vG2 - + vG1 - IT VSS THE SOURCE-COUPLED PAIR - 2 Offset voltage VOS = VG=VG2- VG1 such that ID=I2-I1=0 Simple model ir =0 (sat) The differential input voltage at the input required for ID =0 is Analysis and design of CMOS analog building blocks

  10. I1 I2 M1 M2 + vG2 - + vG1 - IT VSS THE SOURCE-COUPLED PAIR - 3 Uncorrelated  VT &  IS Pelgrom’s model (I) (II) Notes: 0.35 um CMOS technology (I) is dominant over (II) for Analysis and design of CMOS analog building blocks 10

  11. VDD locus vD=vG iD ii io vo iD1 vG + - iD2 M2 M1 + vG - 1:1 vo vD THE TWO-TRANSISTOR CURRENT MIRROR - 1 M1: iv converter M2: vi converter Basic principle VG1=VG2; VS1=VS2; vout>VDsat  ioii Error due to mismatch Error due to difference in VD’s Analysis and design of CMOS analog building blocks

  12. VDD ii ii io C2 io + v - M2 M1 C1 iin io i1 M2 M1 1:A i2 THE TWO-TRANSISTOR CURRENT MIRROR - 2 ac analysis 1:A Noise analysis Uncorrelated noise sources The effect of M1 on noise is A times greater than that of M2 Analysis and design of CMOS analog building blocks

  13. VDD ii io==Aii io==ii/(NM) ...... . . . . . . ii N VDD VDD VDD II IO IO II ...... io==ii/A ii W/L W/L W/L W/L ...... M W/L 1:2 W/L 1/2:1 CURRENT MIRROR: GAIN SCHEMES Gain-of-two current mirrors Gain=A Gain=1/(NM) Gain= 1/A Analysis and design of CMOS analog building blocks

  14. A SELF-BIASED CURRENT SOURCE – 1 Sat. Triode SELF-CASCODE MOSFET (SCM) Applying UICM to both M1 & M2 Analysis and design of CMOS analog building blocks

  15. V-I CHARACTERISTICS OF THE SCM Sat. I2=NIx Triode A SELF-BIASED CURRENT SOURCE – 2 In WI: Analysis and design of CMOS analog building blocks

  16. VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1 A SELF-BIASED CURRENT SOURCE – 3 When both M8 & M9 operate in WI: 1 B. Gilbert, AICSP vol. 38, pp. 83-101, Feb. 2004 Analysis and design of CMOS analog building blocks

  17. A self-biased current source Vx Vx VFCM A SELF-BIASED CURRENT SOURCE – 4 Analysis and design of CMOS analog building blocks

  18. Output current: Iref=10 nA ISHn-channel100 nA, ISHp-channel40 nA A SBCS – 5: DESIGN =1 Let us choose M1 &M2 in MI: if2 = 10 S2= S1, N = 1 =10 nA VFCM M3 &M4 in WI: if3(4) <<1 Let us choose if3=0.187  Analysis and design of CMOS analog building blocks

  19. =1 =10 nA VFCM A SBCS – 6: DESIGN Summary Analysis and design of CMOS analog building blocks

  20. A SBCS – 7 : IOUT vs. VDD AT CONSTANT T Analysis and design of CMOS analog building blocks

  21. Analysis and design of CMOS analog building blocks

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