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CPU Organization (Design)

CPU Organization (Design). Components & their connections needed by ISA instructions. Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic Units, ...)

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CPU Organization (Design)

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  1. CPU Organization (Design) Components & their connections needed by ISA instructions • Datapath Design: • Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions • (e.g., Registers, ALU, Shifters, Logic Units, ...) • Ways in which these components are interconnected (buses connections, multiplexors, etc.). • How information flows between components. • Control Unit Design: • Logic and means by which such information flow is controlled. • Control and coordination of FUs operation to realize the targeted Instruction Set Architecture to be implemented (can either be implemented using a finite state machine or a microprogram). • Hardware description with a suitable language, possibly using Register Transfer Notation (RTN). Control/sequencing of operations of datapath components to realize ISA instructions Chapter 5.1-5.4

  2. Major CPU Design Steps • Analyze instruction set to get datapath requirements: • Using independent RTN, write the micro-operations required for target ISA instructions. • This provides the the required datapath components and how they are connected. • Select set of datapath components and establish clocking methodology (defines when storage or state elements can read and when they can be written, e.g clock edge-triggered) • Assemble datapath meeting the requirements. • Identify and define the function of all control points or signals needed by the datapath. • Analyze implementation of each instruction to determine setting of control points that affects its operations. • Control unit design, based on micro-operation timing and control signals identified: • Combinational logic: For single cycle CPU. • Hard-Wired: Finite-state machine implementation. • Microprogrammed. e.g Any instruction completed in one cycle

  3. CPU Design & Implantation Process • Top-down Design: • Specify component behavior from high-level requirements (ISA). • Bottom-up Design: • Assemble components in target technology to establish critical timing (hardware delays, critical path timing). • Iterative refinement: • Establish a partial solution, expand and improve. Instruction Set Architecture (ISA): Provides Requirements Processor Datapath Control Reg. File Mux ALU Reg Mem Decoder Sequencer Target VLSI implementation Technology Cells Gates

  4. Datapath Design Steps • Write the micro-operation sequences required for a number of representative target ISA instructions using independent RTN. • Independent RTN statements specify: the required datapath components and how they are connected. • From the above, create an initial datapath by determining possible destinations for each data source (i.e registers, ALU). • This establishes connectivity requirements (data paths, or connections) for datapath components. • Whenever multiple sources are connected to a single input, a multiplexor of appropriate size is added. • Find the worst-time propagation delay in the datapath to determine the datapath clock cycle (CPU clock cycle). • Complete the micro-operation sequences for all remaining instructions adding datapath components + connections/multiplexors as needed. (or destination)

  5. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 immediate op rs rt 6 bits 5 bits 5 bits 16 bits 31 26 0 op target address 6 bits 26 bits MIPS Instruction Formats R-Type • op: Opcode, operation of the instruction. • rs, rt, rd: The source and destination register specifiers. • shamt: Shift amount. • funct: Selects the variant of the operation in the “op” field. • address / immediate: Address offset or immediate value. • target address: Target address of the jump instruction. [31:26] [25:21] [20:16] [15:11] [10:6] [5:0] I-Type: ALU Load/Store, Branch [31:26] [25:21] [20:16] [15:0] J-Type: Jumps [31:26] [25:0]

  6. OP rs rd shamt funct rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits MIPS R-Type (ALU) Instruction Fields R-Type: All ALU instructions that use three registers 1st operand 2nd operand Destination • op: Opcode, basic operation of the instruction. • For R-Type op = 0 • rs: The first register source operand. • rt: The second register source operand. • rd: The register destination operand. • shamt: Shift amount used in constant shift operations. • funct: Function, selects the specific variant of operation in the op field. [31:26] [25:21] [20:16] [15:11] [10:6] [5:0] Rs, rt , rd are register specifier fields Independent RTN: R[rd] ¬ R[rs] funct R[rt] PC ¬ PC + 4 Operand register in rs Destination register in rd Operand register in rt add $1,$2,$3 sub $1,$2,$3 and $1,$2,$3 or $1,$2,$3 Examples: R-Type = Register Type Register Addressing used (Mode 1)

  7. 6 bits 5 bits 5 bits 16 bits Examples: add immediate: addi $1,$2,100 and immediate andi $1,$2,10 OP rs immediate rt MIPS ALU I-Type Instruction Fields I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches. • op: Opcode, operation of the instruction. • rs: The register source operand. • rt: The result destination register. • immediate: Constant second operand for ALU instruction. 1st operand Destination 2nd operand [31:26] [25:21] [20:16] [15:0] Independent RTN for addi: R[rt] ¬ R[rs] + immediate PC ¬ PC + 4 Source operand register in rs Result register in rt Constant operand in immediate I-Type = Immediate Type Immediate Addressing used (Mode 2)

  8. 6 bits 5 bits 5 bits 16 bits base register in rs source register in rt Offset OP rs address rt MIPS Load/Store I-Type Instruction Fields Base Src./Dest. (e.g. offset) • op: Opcode, operation of the instruction. • For load word op = 35, for store word op = 43. • rs: The register containing memory base address. • rt: For loads, the destination register. For stores, the source register of value to be stored. • address: 16-bit memory address offset in bytes added to base register. [31:26] [25:21] [20:16] [15:0] Signed address offset in bytes Examples: Mem[R[rs] + address] ¬ R[rt] PC ¬ PC + 4 Store word: sw $3, 500($4) Load word: lw $1, 32($2) R[rt] ¬ Mem[R[rs] + address] PC ¬ PC + 4 base register in rs Destination register in rt Offset Base or Displacement Addressing used (Mode 3)

  9. Examples: Branch on equal beq $1,$2,100 Branch on not equal bne $1,$2,100 OP rs address rt MIPS Branch I-Type Instruction Fields (e.g. offset) • op: Opcode, operation of the instruction. • rs: The first register being compared • rt: The second register being compared. • address: 16-bit memory address branch target offset in words added to PC to form branch address. 6 bits 5 bits 5 bits 16 bits [31:26] [25:21] [20:16] [15:0] Signed address offset in words Register in rt offset in bytes equal to instruction address field x 4 Register in rs Added to PC+4 to form branch target Independent RTN for beq: R[rs] = R[rt] : PC ¬ PC + 4 + address x 4 R[rs] ¹ R[rt] : PC ¬ PC + 4 PC-Relative Addressing used (Mode 4)

  10. OP jump target 6 bits 26 bits Examples: Jump j 10000 Jump and link jal 10000 0 0 jump target = 2500 4 bits 26 bits 2 bits MIPS J-Type Instruction Fields J-Type: Include jump j, jump and link jal • op: Opcode, operation of the instruction. • Jump j op = 2 • Jump and link jal op = 3 • jump target: jump memory address in words. Jump target in words [31:26] [25:0] Jump memory address in bytes equal to instruction field jump target x 4 Effective 32-bit jump address: PC(31-28),jump_target,00 PC(31-28) From PC+4 Independent RTN for j: PC ¬ PC + 4 PC ¬ PC(31-28),jump_target,00 J-Type = Jump Type Pseudodirect Addressing used (Mode 5)

  11. 31 26 21 16 11 6 0 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits A Subset of MIPS Instructions ADD and SUB: add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm16 LOAD and STORE Word lw rt, rs, imm16 sw rt, rs, imm16 BRANCH: beq rs, rt, imm16 [31:26] [25:21] [20:16] [15:11] [10:6] [5:0] [31:26] [25:21] [20:16] [15:0] [31:26] [25:21] [20:16] [15:0] [31:26] [25:21] [20:16] [15:0]

  12. Instruction Fetch Next Instruction Instruction Decode Execute Result Store Basic MIPS Instruction Processing Steps Instruction Memory } Obtain instruction from program storage Instruction ¬ Mem[PC] Common steps for all instructions Update program counter to address of next instruction PC ¬ PC + 4 Determine instruction type Obtain operands from registers Done by Control Unit Compute result value or status Store result in register/memory if needed (usually called Write Back).

  13. Overview of MIPS Instruction Micro-operations • All instructions go through these common steps: • Send program counter to instruction memory and fetch the instruction. (fetch) Instruction ¬ Mem[PC] • Update the program counter to point to next instruction PC ¬ PC + 4 • Read one or two registers, using instruction fields. (decode) • Load reads one register only. • Additional instruction execution actions (execution) depend on the instruction in question, but similarities exist: • All instruction classes use the ALU after reading the registers: • Memory reference instructions use it for address calculation. • Arithmetic and logic instructions (R-Type), use it for the specified operation. • Branches use it for comparison. • Additional execution steps where instruction classes differ: • Memory reference instructions: Access memory for a load or store. • Arithmetic and logic instructions: Write ALU result back in register. • Branch instructions: Change next instruction address based on comparison.

  14. CPU Performance Equation: T = I x CPI x C A Single Cycle MIPS CPU Design Design target: A single-cycle per instruction MIPS CPU design All micro-operations of an instruction are to be carried out in a single CPU clock cycle. Cycles Per Instruction = CPI = 1 Abstract view of single cycle MIPS CPU showing major functional units (components) and major connections between them CPI = 1 Figure 5.1 page 287

  15. OP rs rd shamt funct rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-Type Example:Micro-Operation Sequence For ADD Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC R[rd] ¬ R[rs] + R[rt] Add register rs to register rt result in register rd add rd, rs, rt [31:26] [25:21] [20:16] [15:11] [10:6] [5:0] Common Steps Program Memory Independent RTN ?

  16. 32 32 32 32 32 32 Instruction Word 32 Initial Datapath Components Three components needed by: Instruction Fetch:Instruction ¬ Mem[PC] Program Counter Update:PC ¬ PC + 4 • Two state elements (memory) needed to store and access instructions: • Instruction memory: • Only read access (by user code). No read control signal needed. • Program counter (PC): 32-bit register. • Written at end of every clock cycle (edge-triggered) : No write control signal. • 32-bit Adder: To compute the the next instruction address (PC + 4). Basics of logic design/logic building blocks review in Appendix B (Book CD)

  17. 32 32 32 32 32 More Datapath Components ISA Register File Main 32-bit ALU 4 32-bit Arithmetic and Logic Unit (ALU) • Register File: • Contains all ISA registers. • Two read ports and one write port. • Register writes by asserting write control signal • Clocking Methodology:Writes are edge-triggered. • Thus can read and write to the same register in the same clock cycle. Basics of logic design/logic building blocks review in Appendix B (Book CD)

  18. RW RA RB Write Enable 5 5 5 busA busW 32 32 32-bit Registers 32 busB Clk 32 Register File Details • Register File consists of 32 registers: • Two 32-bit output busses: busA and busB • One 32-bit input bus: busW • Register is selected by: • RA (number) selects the register to put on busA (data): busA = R[RA] • RB (number) selects the register to put on busB (data): busB = R[RB] • RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1 Write Enable: R[RW] ¬ busW • Clock input (CLK) • The CLK input is a factor ONLY during write operations. • During read operation, it behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.”

  19. Register Write Enable (RegWrite) . . 32 0 1 . RW RA RB Write Enable 5 5 5 busA Write Write Write Write Data Out Data Out Data Out Data Out 32 Register 31 Register 0 Register 30 Register 1 busW . . . 32 32 32-bit Registers . 32 Data In Data In Data In Data In 32 busB Register Read Data 1 (Bus A) 0 Clk Write Register RW 32 . 32-to-1 MUX 32-to-1 MUX 1 . 30 31 . . . . 5 5-to-32 Decoder . . . . . . Read Register 1 (RA) . 32 30 0 1 31 . 5 32 . . . 32 32 Register Read Data 2 (Bus B) . 30 31 Register Write Data (Bus W) 5 Read Register 2 (RB) A Possible Register File Implementation Each Register contains 32 edge triggered D-Flip Flops Clock input to registers not shown in diagram Also see Appendix B (Book CD) - The Basics of Logic Design

  20. Write Enable Address Data In DataOut 32 32 Clk Idealized Memory • Memory (idealized) • One input bus: Data In. • One output bus: Data Out. • Memory word is selected by: • Address selects the word to put on Data Out bus. • Write Enable = 1: address selects the memoryword to be written via the Data In bus. • Clock input (CLK): • The CLK input is a factor ONLY during write operation, • During read operation, this memory behaves as a combinational logic block: • Address valid => Data Out valid after “access time.” • Ideal Memory = Short access time.

  21. . . . . . . . . . . . . Clocking Methodology Used:Edge Triggered Writes • All storage element (e.g Flip-Flops, Registers, Data Memory) writes are triggered by the same clock edge. • Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Clk Setup Hold Setup Hold Don’t Care Critical Path Here writes are triggered on the rising edge of the clock

  22. 32 32 32 32 Building The Datapath PC ¬ PC + 4 Instruction Fetch & PC Update: Instruction ¬ Mem[PC] Portion of the datapath used for fetching instructions and incrementing the program counter. PC write or update is edge triggered at the end of the cycle

  23. 32 32 32 32 Simplified Datapath For MIPS R-Type Instructions rs 4 [25:21] [20:16] [15:11] From Instruction Memory R[rs] rt rd R[rt] Components and connections as specified by RTN statement R[rd] ¬ R[rs] + R[rt] Destination register R[rd] write or update is edge triggered at the end of the cycle

  24. Rd Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32 More Detailed Datapath For R-Type InstructionsWith Control Points Identified R[rs] R[rt] R[rd] ¬ R[rs] + R[rt]

  25. Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value RegWr Old Value New Value Register File Access Time busA, B Old Value New Value ALU Delay busW Old Value New Value Rd Rs Rt Register Write Occurs Here ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32-bit Registers Result ALU 32 32 busB Clk 32 R-Type Register-Register Timing PC+4 All register writes occur on falling edge of clock (clocking methodology)

  26. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Logical Operations with Immediate Example:Micro-Operation Sequence For ORI Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC R[rt] ¬ R[rs] OR ZeroExt[imm16] OR register rs with immediate field zero extended to 32 bits, result in register rt ori rt, rs, imm16 [31:26] [25:21] [20:16] [15:0]

  27. 1 0 Rd Rt RegDst Mux Rs Rt ALUctr RegWr 5 5 5 busA Rw Ra Rb busW 32 Result 32 32-bit Registers ALU 32 32 busB Clk 32 Mux ZeroExt imm16 32 16 ALUSrc Datapath For Logical Instructions With Immediate 2x1 MUX (width 5 bits) R[rs] R[rt] 2x1 MUX (width 32 bits) R[rt] ¬ R[rs] OR ZeroExt[imm16]

  28. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Load Operations Example:Micro-Operation Sequence For LW Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC R[rt] ¬ Mem[R[rs] + SignExt[imm16]] Immediate field sign extended to 32 bits and added to register rs to form memory load address, write word at load effective address to register rt lw rt, rs, imm16 Address offset in bytes [31:26] [25:21] [20:16] [15:0] Instruction Memory Effective Address Data Memory

  29. 32 32 32 Additional Datapath Components For Loads & Stores For SignExt[imm16] Inputs: for address and write (store) data Output for read (load) data 16-bit input sign-extended into a 32-bit value at the output Data memory write or update is edge triggered at the end of the cycle (clocking methodology)

  30. Rd Rt RegDst 0 1 Mux Rs ALUctr RegWr 5 5 5 Base Address register MemtoReg R[rs] busA Rw Ra Rb Effective Address busW 32 32 32-bit Registers ALU 32 0 32 R[rt] busB Clk MemWr 0 32 Mux Mux WrEn Adr Offset Data In 1 32 1 Data Memory Extender 32 imm16 32 16 Clk ALUSrc ExtOp Datapath For Loads R[rt] ¬ Mem[R[rs] + SignExt[imm16]]

  31. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Store Operations Example:Micro-Operation Sequence For SW Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC Mem[R[rs] + SignExt[imm16]] ¬ R[rt] Immediate field sign extended to 32 bits and added to register rs to form memory store effective address, register rt written to memory at store effective address. sw rt, rs, imm16 Address offset in bytes Effective Address

  32. Rd Rt MemtoReg ALUctr MemWr RegDst 0 1 Mux Rs Rt RegWr 5 5 5 Base Address register R[rs] busA Rw Ra Rb Effective Address busW 32 32 32-bit Registers ALU 0 32 32 R[rt] busB Clk 0 32 Mux Mux R[rt] WrEn Adr Offset Data In 32 1 32 Data Memory 1 Extender imm16 32 16 Clk ALUSrc ExtOp Datapath For Stores Mem[R[rs] + SignExt[imm16]] ¬ R[rt]

  33. 31 26 21 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Conditional Branch Example:Micro-Operation Sequence For BEQ Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC Zero ¬ R[rs] - R[rt] Calculate the branch condition R[rs] == R[rt] (i.e R[rs] - R[rt] = 0 ) Zero : PC ¬ PC + ( SignExt(imm16) x 4 ) Calculate the next instruction’s PC address beq rs, rt, imm16 PC Offset in words [31:26] [25:21] [20:16] [15:0] Condition Action Branch Target “Zero” is zero flag of main ALU

  34. Main ALU evaluates branch condition • New adder to compute branch target: • Sum of incremented PC and the • sign-extended lower 16-bits on the • instruction. Datapath For Branch Instructions New 32-bit Adder (Third ALU) for Branch Target ( SignExt(imm16) x 4 PC + 4 + ( SignExt(imm16) x 4 [25:21] rs [20:16] rt R[rs] R[rt] Zero flag =1 if R[rs] - R[rt] = 0 (i.e R[rs] = R[rt]) Main ALU Evaluates Branch Condition (subtract) [15:0] imm16 SignExt(imm16)

  35. 32 Branch Zero Instruction Address Zero PCSrc Rs Rt 32 PC+4 4 RegWr 5 5 5 0 00 busA Adder Rw Ra Rb busW 32 32 32-bit Registers Equal? PC Mux PC busB 1 Clk Main ALU (subtract) 32 imm16 Branch Target Adder PC Ext Clk New 2X1 32-bit MUX to select next PC value Branch Target ALU Sign extend shift left 2 More Detailed Datapath For Branch Operations

  36. Combining The Datapaths For Memory Instructions and R-Type Instructions 4 [25:21]rs R[rs] [20:16]rt R[rt] 0 1 1 0 R[rt] rt/rd MUX not shown SignExt(imm16) [15:0] imm16 Highlighted muliplexors and connections added to combine the datapaths of memory and R-Type instructions into one datapath (This is book version ORI not supported)

  37. Instruction Fetch Datapath Added toALU R-Type and Memory Instructions Datapath PC+ 4 PC rs 4 R[rs] rt R[rt] 0 1 1 0 rt/rd MUX not shown (This is book version ORI not supported, no zero extend of immediate needed)

  38. PC +4 Branch Target 0 1 1 0 rt/rd MUX not shown A Simple Datapath For The MIPS Architecture • Datapath of branches and a program counter multiplexor are added. • Resulting datapath can execute in a single cycle the basic MIPS instruction: • - load/store word - ALU operations - Branches 4 (This is book version ORI not supported, no zero extend of immediate needed) Figure 5.11 page 300

  39. ALU Control Lines ALU Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 Set-on-less-than 1100 NOR Main ALU Control • The main ALU has four control lines (detailed design in Appendix B) with the following functions: • For our current subset of MIPS instructions only the top five functions will be used (thus only three control lines will be used) • For R-type instruction the ALU function depends on both the opcode and the 6-bit “funct” function field • For other instructions the ALU function depends on the opcode only. • A local ALU control unit can be designed to accept 2-bit ALUop control lines (from main control unit) and the 6-bit function field and generate the correct 4-bit ALU control lines.

  40. Instruction Opcode LW SW Branch Equal R-Type R-Type R-Type R-Type R-Type Instruction Operation Load word Store word branch equal add subtract AND OR set on less than ALUOp 00 00 01 10 10 10 10 10 Funct Field XXXXXX XXXXXX XXXXXX 100000 100010 100100 100101 101010 Desired ALU Action add add subtract add subtract and or set on less than ALU Control Lines 0010 0010 0110 0010 0110 0000 0001 0111 func ALUctr op 6 Main Control 4 ALU Control (Local) ALUop 6 2 ALU Local ALU Decoding of “func” Field

  41. Local ALU Control Unit (2 lines From main control unit) Function Field 3 ALU Control Lines More details found in Appendix C (Book CD)

  42. Single Cycle MIPS Datapath Necessary multiplexors and control lines are identified here and local ALU control added: Function Field (2 bits) (This is book version ORI not supported, no zero extend of immediate needed) Figure 5.15 page 305

  43. Inst Memory ALU Control Adr Branch Zero Adder Mux Adder Putting It All Together: A Single Cycle Datapath Instruction<31:0> <0:15> <21:25> <16:20> <11:15> ALUop (2-bits) Rs Rt Rd Imm16 PCSrc RegDst MemWr MemtoReg Function Field Zero Rt Rd 0 1 Rs Rt 4 PC+4 RegWr 5 5 5 Main ALU R[rs] busA Rw Ra Rb = 0 busW 00 32 32 32-bit Registers R[rt] ALU 0 32 busB 32 0 PC 32 Mux Mux 1 Clk 32 WrEn Adr 1 Clk 1 Data In Data Memory Extender imm16 PC Ext 32 Branch Target 16 imm16 Clk ExtOp ALUSrc (Includes ORI not in book version)

  44. Instruction<31:0> Instruction Memory <21:25> <0:25> <21:25> <16:20> <11:15> <0:15> Adr Op Fun Jump_target Rt Rs Rd Imm16 Control Unit Control Lines ALOp (2-bits) Mem Write Mem Read MemtoReg Branch ALUSrc RegWrite RegDst DATA PATH

  45. The Effect of The Control Signals Signal Name RegDst RegWrite ALUSrc PCSrc MemRead MemWrite MemtoReg Effect when deasserted (=0) The register destination number for the write register comes from the rt field (instruction bits 20:16). None The second main ALU operand comes from the second register file output (Read data 2) R[rt] The PC is replaced by the output of the adder that computes PC + 4 None None The value fed to the register write data input comes from the main ALU. Effect when asserted (=1) The register destination number for the write register comes from the rd field (instruction bits 15:11). The register on the write register input is written with the value on the Write data input. The second main ALU operand is the sign-extended lower 16 bits on the instruction (imm16) The PC is replaced by the output of the adder that computes the branch target. Data memory contents designated by the address input are put on the Read data output. Data memory contents designated by the address input are replaced by the value on the Write data input. The value fed to the register write data input comes from data memory.

  46. Instruction R-Format lw sw beq RegDst 1 0 X X ALUSrc 0 1 1 0 Memto- Reg 0 1 X X Reg Write 1 1 0 0 Mem Read 0 1 0 0 Mem Write 0 0 1 0 Branch 0 0 0 1 ALUOp1 1 0 0 0 ALUOp0 0 0 0 1 Control Line Settings Figure 5.18 page 308

  47. The Truth Table For The Main Control (Opcode)

  48. PLA Implementation of the Main Control Figure C.2.5 (Appendix C) PLA = Programmable Logic Array (Appendix B)

  49. OP Jump_target 6 bits 26 bits 0 0 jump target = 2500 4 bits 26 bits 2 bits Adding Support For Jump:Micro-Operation Sequence For Jump: J Instruction Word ¬ Mem[PC] Fetch the instruction PC ¬ PC + 4 Increment PC PC ¬ PC(31-28),jump_target,00 Update PC with jump address j jump_target Jump address in words [31:26] [25:0] PC(31-28) Jump Address 4 highest bits from PC + 4

  50. Branch Zero 32 32 32 28 26 4 4 Adder Mux Mux PC Adder jump_target Shift left 2 Clk Datapath For Jump Next Instruction Address PCSrc JUMP PC+4 32 00 0 PC Instruction(15-0) 1 Branch Target imm16 PC Ext Jump Address PC+4(31-28) PC(31-28),jump_target,00 Instruction(25-0)

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