Simultaneous Perturbation Learning Rule for Recurrent Neural Networks and Its FPGA Implementation

1. 國立臺灣海洋大學 National Taiwan Ocean University Simultaneous Perturbation Learning Rule for Recurrent Neural Networks and Its FPGA Implementation 通訊與導航工程學系 Department of Communication, Navigation and Control Engineering 老師:曾慶耀 學生：王家安

2. References • This paper appears in:Neural Networks, IEEE Transactions onIssue Date: Nov. 2005 Volume: 16 Issue:6On page(s): 1664 - 1672 ISSN: 1045-9227 References Cited: 28 Cited by : 13INSPEC Accession Number: 8649235 Digital Object Identifier:10.1109/TNN.2005.852237Date of Current Version: 07 十一月 2005 PubMed ID: 16342505Sponsored by:IEEE Computational Intelligence Society

3. Outline • INTRODUCTION • LEARNING SCHEME USING SIMULTANEOUS PERTURBATION • FPGA IMPLEMENTATION OF HNN A. Technical Factors B. HNN System C. Result • CONCLUSION

4. Introduction • 1) We summarize the learning scheme using the simultaneousperturbation for RNNs. • 2) We design an FPGA HNN system as a typical exampleof RNN systems. Then it is important to take inherentrecurrent signal flows into account. • 3) Learning capability via the simultaneous perturbationis realized using FPGA as a hardware system. • 4) We consider an analog HNN. Then ordinary arithmeticoperations are used to realize neural signal processing,instead of Boolean operations such as OR or AND usedin a pulse stream type of implementation .

5. Outline • INTRODUCTION • LEARNING SCHEME USING SIMULTANEOUS PERTURBATION • FPGA IMPLEMENTATION OF HNN A. Technical Factors B. HNN System C. Result • CONCLUSION

6. LEARNING SCHEME USING SIMULTANEOUS PERTURBATION

7. LEARNING SCHEME USING SIMULTANEOUS PERTURBATION

8. Outline • INTRODUCTION • LEARNING SCHEME USING SIMULTANEOUS PERTURBATION • FPGA IMPLEMENTATION OF HNN A. Technical Factors B. HNN System C. Result • CONCLUSION

9. FPGA IMPLEMENTATION OF HNN • 1) Representation of Numerical Values and Operations: IEEE 754 • 2) Control Unit: A. Technical Factors

10. FPGA IMPLEMENTATION OF HNN • 3) Neuron Unit: A. Technical Factors

11. FPGA IMPLEMENTATION OF HNN • 4) Learning Unit: Error part A. Technical Factors

12. FPGA IMPLEMENTATION OF HNN Modification part A. Technical Factors

13. FPGA IMPLEMENTATION OF HNN • 5) Memory: Memory stores the weight values of the neurons, the output and weight values of the neurons, the sign information, and the teaching signals. These data are read or restored according to the command of the control unit. A. Technical Factors

14. FPGA IMPLEMENTATION OF HNN B. HNN System

15. FPGA IMPLEMENTATION OF HNN 1) Analog Pattern: C. Result

16. FPGA IMPLEMENTATION OF HNN 2) Oscillatory Solution: C. Result

17. Outline • INTRODUCTION • LEARNING SCHEME USING SIMULTANEOUS PERTURBATION • FPGA IMPLEMENTATION OF HNN A. Technical Factors B. HNN System C. Result • CONCLUSION

18. Conclusions • This paper proposed a recursive learning scheme for recurrentNNs. The learning scheme is based on the simultaneous perturbationmethod. • As an example, we implement the HNN with this learningscheme by FPGA. Learning examples for analog targets and anoscillatory pattern are shown. • This scheme requires only two values of an error function.Therefore, it was relatively easy to implement, especially as ahardware system. • Moreover, it is possible to utilize this scheme for analog problemsor the learning of oscillatory patterns in contrast to ordinaryHebbianlearning.

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21. 序率坡降法 • 以最陡坡降法的觀念搜尋瞬時目標函數，來修正隱藏層的中心點位置(ci) 、幅狀基底函數的形狀(ci)和輸出層權重(wi)可視為線上學習演算法。 • 瞬時目標函數： • 中心點： • 標準偏差： • 輸出權重：