EMCAL jet trigger status

1. Olivier BOURRION LPSC, Grenoble EMCAL jet trigger status Alice EMCAL meeting, 15-16 July 2008

2. Alice EMCAL meeting, 15-16 July 2008 Reminder : the Summary Trigger Unit TTC link TRU L0 STU L1-gamma To CTP 34 TRU LVDS links L1-jet DDL 4 diff pair Ethernet CAT7 cable TRU DCS Put trigger data in the data stream on L2a (via DDL)‏ TRU is clocked by the BC clock forwarded by STU (40.08MHz)‏ Multiplicity from V0 • Trigger specification : • L0 trigger : OR of the 34 L0 calculated by the TRU. • L1-gamma trigger: Energy summed over sliding window of 4x4 towers (2x2 fast OR) and compared to a multiplicity corrected threshold. • L1-jet trigger : Energy summed over a sliding window of n*n subregions and compared to a multiplicity corrected threshold (a subregion is defined as 8x8 towers)‏

3. Detector layout as understood Alice EMCAL meeting, 15-16 July 2008

4. Alice EMCAL meeting, 15-16 July 2008 EMCAL layout (1/2)‏ The understanding of the layout is the key point for building the trigger algorithm Region orientation / numbering? View from beam or cal frame? Mirrored SM

5. Alice EMCAL meeting, 15-16 July 2008 EMCAL layout for one TRU (2/2)‏ ? Confirmation of the ADC channel affectation vs geometrical position The ADC channel number has to be known by STU, in order to compute the triggers For instance, one 4X4 window is channel 5,6,9 and 10

6. Alice EMCAL meeting, 15-16 July 2008 Functional simulation scenario(see R. GUERNANE talk) 3 2 1 Overlapping 2 neighboring regions in phi Overlapping 2 neighboring regions in Z Overlapping 4 regions

7. Current status Alice EMCAL meeting, 15-16 July 2008

8. Alice EMCAL meeting, 15-16 July 2008 DCS board modification and testing The transformer less Ethernet board was tested at LCMI in march 2008 No packet loss @ 0.53 T

9. Alice EMCAL meeting, 15-16 July 2008 Thermal study results(work done by Julien GIRAUD : julien.giraud@lpsc.in2p3.fr) 2 mm copper plate • Problem: board will dissipate nearly 36 W • Assumptions: • water flow 20°C, tube =5 mm, Q= 1l/min • Hot component coupled with a 2 mm copper plate via a thermal foam • hottest spot 36°C (conservative, convection neglected)

10. Alice EMCAL meeting, 15-16 July 2008 Actual STU board layout For TRU: Dual stacked RJ45. 10 on left side, 20 on front, 10 on right side

11. Alice EMCAL meeting, 15-16 July 2008 Summary of the STU status • Work done so far • LVDS Link validation (july 07) • DCS hardware modification and qualification • Thermal study • PVSS and DCS know-how gained by G. DARGAUD on Pixel trigger • Some VHDL available (deserializer, TTCrq interface)‏ • Board layout, fabrication in progress (board received july 11th) • To do • VHDL design: • final VHDL • degraded versions for tests (TRU link only, limited L1-gamma, L1-jet). This has to be defined • TRU link validation (to be discussed)‏ • Interfaces tests and validation (DDL, V0, TTC)‏ • PVSS driver for Emcal

12. Alice EMCAL meeting, 15-16 July 2008 Testing tools USB LVDS USB Slow control LVDS TRU CAT7 LVDS cable 15m STU Proposed TRU-STU link validation methodology • An emitting buffer is loaded via the testing tools • A frame transfer is initiated • The receiving buffer is read by the testing tools Above steps have to be repeated many times with different packet contents. This scheme will exercise the link as in the final design. • This is somewhat similar to the tests performed in july 2007 on the TOR board • Has to be performed before TRU full production order (September 08??)

13. Alice EMCAL meeting, 15-16 July 2008 SPARES

14. Alice EMCAL meeting, 15-16 July 2008 Available L1 processing time L1 emission deadline (at STU ouput)‏ L1 reception deadline (at CTP input)‏ STU forward one L0 to CTP interaction TRU start of transmission One or several TRU sends L0 to STU L0 from CTP at RCU All data in STU Available 2745 ns (PHOS)‏ Available 2985 ns (EMCAL)‏ t 0 ns 600 ns 700 ns 1200 ns 6100 ns 1400 ns 3155 ns 5900 ns PHOS: 112*12 bit/800Mbs+75ns=1.755µs EMCAL: 96*12 bit/800Mbs+75ns=1.515µs 75ns : estimated 15m of wire PHOS: 112*12 bit/800Mbs+75ns=1.755µs EMCAL: 96*12 bit/800Mbs+75ns=1.515µs 75ns : estimated 15m of wire 200ns : estimated 40m of wire

15. Alice EMCAL meeting, 15-16 July 2008 L1-gamma processing (1/2)‏ A region R region A+1,R+1 region Now the numbers are the readout order Column are read top to bottom and then row right to left Refering to the previous slide DPRAM readout is 4,3,1,2,8,7,5,6,…

16. Alice EMCAL meeting, 15-16 July 2008 L1-gamma processing (2/2)‏ The trigger is computed for each region, with neighboring region inputs. Requires 4 accumulators (col size) X 2 (window size)‏ Latency is roughly 100 X 1/120MHz~900 ns

17. Alice EMCAL meeting, 15-16 July 2008 L1-jet processing (1/2)‏ Based on P. Jacobs proposal: 6 subregions are created in each region. Below subregion delimitation, 4x4 fast OR  8x8=64 towers Numbers are the readout order and not the ADC channel number Total: 204 subregions Each subregion energy sum is computed in parallel with L1-gamma 6 accumulators (no overlapping)  latency ~900 ns

18. Alice EMCAL meeting, 15-16 July 2008 L1-jet processing (2/2)‏ The algorithm to apply is somewhat similar to L1-gamma except that here the columns contains 12 elements  No accumulators for 1 subregion patch, direct threshold comparison 12*2 accumulators for a 2X2 subregion patch 12*3 accumulators for 3X3 subregion patch Latency: >204 clock cycles  >1.7µs (remaining margin: 2.985-1.7-0.9=385ns)‏