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9U FEDv1 New Production

9U FEDv1 New Production. Assembly of 6 boards FEDv1 design by DDi Technologies (pcbs Ni/Au finish by DDi Tewksbury) Received 4 boards on schedule (remaining 2 coming this week). At Assembly company : Advanced QA procedures

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9U FEDv1 New Production

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  1. 9U FEDv1 New Production Assembly of 6 boards FEDv1 design by DDi Technologies (pcbs Ni/Au finish by DDi Tewksbury) Received 4 boards on schedule (remaining 2 coming this week). At Assembly company : Advanced QA procedures Automated Optical Inspection, Ersa-scope & X-ray on BGAs, Takaya Flying probe. At RAL: Digital circuit checks: Boundary Scan on all 4 boards excellent: 2 without errors; one with 1 error (fixed); 1 with few TTCrx errors Analogue circuit checks: VME Readout Tests with Opto inputs : All 4 boards look good on all 96 channels (change requested for new ADC operation needs to be added to 3 of these boards, simple mod). Peripheral chip tests EPROM, Temp sensors etc.. look ok, except TTCrx on 2 boards failing I2C comms. New pcb impedances need verifying for signal timing. Conclusion: Good QA procedures. Good quality boards. http://www.te.rl.ac.uk/esdg/cms-fed

  2. FEDv1 Firmware Major Activities to verify FEDv1 Design: Done • Front-End FPGA Algorithms : “Baseline” algorithms (flat CM) now tested and working. • S-LINK : Test fast readout logic using DAQ FEDKit. 100kHz random trigger data transfers now working reliably; 64 bits @ 80MHz. BERs being measured. • SPY Channel : Copy of raw data via VME for checking zero suppression is working. • Peripherals : EPROM for holding permanent data working. Temperature & Voltage monitoring devices working. • FPGA in-situ reprogramming: Compact Flash card holding permanent FPGA configurations can now be re-programmed in-situ over network. To do... • TTCrx ChanB: Transfers from APVE under test. http://www.te.rl.ac.uk/esdg/cms-fed

  3. CMS Tracker FED Firmware Status 15th March 2004 System ACE EPROM VME FPGA Ed->Saeed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC VME Clocks I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Data Input Serial Comms VME LINK Spy Data Header Mode Header Mode Cluster Mode Input Ed->Saeed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Saeed To be Implemented Control S-LINK S-LINK Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2 http://www.te.rl.ac.uk/esdg/cms-fed

  4. CMS Tracker FED Firmware Status 4th November 2003 System ACE EPROM VME FPGA Ed->Saeed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC VME Clocks I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Data Input Serial Comms VME LINK Spy Data Header Mode Header Mode Cluster Mode Input Ed->Saeed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Saeed To be Implemented Control S-LINK S-LINK Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2 http://www.te.rl.ac.uk/esdg/cms-fed

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