Conformal computing program july 26 2007
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Conformal Computing Program July 26, 2007. NDSU Center for Nanoscale Science & Engineering. Center for Bits and Atoms MIT Media Lab. CNSE CC Team. (not pictured: Ahana Gosh and Jordan Dahl). Wallpaper Computing Display. Extensible Medium Integrated Computation and Display

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Conformal Computing Program July 26, 2007

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Conformal computing program july 26 2007

Conformal Computing ProgramJuly 26, 2007

NDSU Center for Nanoscale Science & Engineering

Center for Bits and Atoms

MIT Media Lab

Cnse cc team


(not pictured: Ahana Gosh and Jordan Dahl)

Wallpaper computing display

Wallpaper Computing Display

  • Extensible Medium

  • Integrated Computation and Display

  • Flexible Substrate

  • Similarities to Wallpaper

Wcd prototypes

WCD Prototypes

  • Rigid 2x2 and 8x8 Prototypes

  • Strip Concept

  • Strip Prototypes

2x2 prototype

2x2 Prototype

Each processor scans 48 leds

Each processor scans 48 LEDs …

Processor + R’s + C

4 x 4 RGB Pixels

And connects to 4 neighbors

… and connects to 4 neighbors.

8x8 prototype 1 processor and 16 pixels cm 2

8x8 Prototype (1 processor and 16 pixels / cm2)

computing side display side



Strip concept

Strip Concept

  • Uses only two metal layers  Lower cost, thinner, more flexible

  • Strips combine to form sheets  Extensible

1x8 strip layout

1x8 Strip Layout

Layer 1 (display side)

Layer 2 (computing side)

2 nd strip prototype

2nd Strip Prototype

computing side display side

Flat strip display

Flat Strip Display

  • Top: thin 2-layer boards

  • Bottom: thick multi-layer boards

  • Must include processor-to-display cxns

  • No vias in strip-to-strip power distribution



  • Application Services

  • CA Emulation

  • Distributed Graphics

  • Interactive I/O

  • Tactile Array

  • LED Camera

Application services

Application Services

  • Provides common application functions

  • Functions include:

    • Initial program loading (IPL)

    • Display setting and refreshing

    • Inter-processor communication (IPC)

    • Message passing

    • Thread management

    • Subsequent program loading

Ca emulation

CA Emulation

  • Each cell has 8 configuration bits and 1 state bit

  • A text file format has been defined to specify the configurations and initial states of an array of cells

  • The text file is used to define the program to be loaded into a wallpaper computing display

  • A message passing sequence is used to exchange data between the subarrays emulated by individual processors

Distributed graphics

Distributed Graphics

  • Purpose

    • Explore distributed applications capabilities using the 2x2 and 8x8 prototypes

  • Objective

    • Render a single graphics primitive (a quadrilateral) in a distributed fashion



  • Load all processors with same program

  • Inject a message into the array via one of the peripheral processors; the message describes the primitive to be rendered

  • Each processor renders a sub-image and passes a copy of the message to two of its neighbors

  • Duplicate messages are discarded



A (a1, a2)

B (b1, b2)

border pixel

D (d1, d2)

outside pixel

inside pixel

C (c1, c2)

Controller and 8x8 wcd

Controller and 8x8 WCD

Tactile array

Tactile Array


Produce an example of actuation integrated with a conformal computer


Tactile array for sensory substitution

Tactile display prototype

Tactile Display Prototype

Testbed for tactile transduction on forehead; uses biofeedback

Sensor system

Ultrasound range finders in fly’s eye configuration

Accurate 3.5 meter range sensing

Display system

Electromechanical actuators


3 microcontrollers in master-slave configuration

Tactile display schematic

Tactile Display Schematic

Stepper motor brush

Transduction produced by brush on plastic disk

Stepper motor driven by

Pulse-width modulation

Short envelope duty cycle


No audible noise

Relatively low power

Stepper Motor & Brush

Led camera

LED Camera

Programmable cellular arrays

Programmable Cellular Arrays

  • (Larger Arrays of Microcontrollers)

  • Programmable Cellular Array ASIC

  • Assembling Large Arrays of ASICs

  • (Using the 3rd Dimension)

Ca processors

CA Processors

  • Purpose

    • Scale processors down in size (and complexity) and up in number

  • Objectives

    • Design CMOS ASICs with arrays of simple computational cells

    • Consider sync & async approaches

Single ca cell

Single CA Cell

Assembly methods

Assembly Methods

  • Via-to-Pad

  • Roll-to-place (Part Printer)

  • FSA

  • R2R Flip-Chip on Flex

  • Selective Device Transfer

Via to pad


Roll to place


  • Parts are “printed” from dispensers

  • Dispensers are at fixed locations relative to the roll

  • (See MIT-CBA for dispenser mock-up)



Fsa process

FSA Process

R2r flip chip on flex automated assembly corporation

R2R Flip-Chip on Flex Automated Assembly Corporation

Selective device transfer figure from www zurich ibm com st server selectivetrans html

Selective Device TransferFigure from

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