1 / 13

Proposal for Gaspard Front-end electronics

This proposal outlines the ASIC design and issues for the front-end electronics of Gaspard, including options for annular detectors and trapezoidal shapes. It also discusses the telescope structure, channels and output signals, multiplexing, power consumption, and an ASIC for pulse shaping.

ccharlotte
Download Presentation

Proposal for Gaspard Front-end electronics

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Proposal for Gaspard Front-end electronics E. Rauly, V.Chambert Valérie Chambert, IPNO, 29 juin 2012

  2. Outline ASIC design Front-end proposal and issues Valérie Chambert, IPNO, 29 juin 2012

  3. Option: Annular detectors Gaspard Trapezoidal shapes for endcaps Square : 2 silicon layers BACKWARD : 2 silicon layers FORWARD : 3 silicon layers Valérie Chambert, IPNO, 16 février 2012

  4. Telescope structure forward 1.5mm 32 N + 32 P (E, t) 1.5mm 32 N + 32 P (E, t) 300(500)µm 128 N (E, t) + 128 P (PSA, E, i) P.Rosier Valérie Chambert, IPNO, 16 février 2012

  5. Channels and output signals (1) • Channels : • (128+128)x22 1 layer • (64+64)x8 2nd/3rd layer forward • 64x8 2nd layer backward • 64x6 2nd layer square Valérie Chambert, IPNO, 16 février 2012

  6. Channels and output signals (2) • 128 PSA (i+Q outputs)x (8+8+6) = 5632 fast digitisation P • 128 x2X22= 5632 N (E, t) • 64x2 layersx8trapezesx2outputs + (forward) 64x1 layersx8trapezesx2outputs + (backward) 64x1couchex6 squares x 2sorties (square) • 15104 outputs if we don’t multiplex Valérie Chambert, IPNO, 16 février 2012

  7. Multiplexing • Total 15104 = 5632 PSA + 9472 (E or t) • If we multiplex by 16 the (E, t) we get : 5632 + 592 output cables = 6224 cables • If we multiplex by 16 (E, t) AND Q from 1st layer P zone, we get : 2816 (i PSA) + 176 (Q) + 592 = 3584 cables Question : can we save PSA for Q outputs ? Note : few embedded FPGA would drastically reduce the i PSA cables from 2816 to few Valérie Chambert, IPNO, 16 février 2012

  8. Power consumption for i and Q PSA • 5632x(15mW ampli+ADC100mW) = 650 W • E or t PC: 9472 x5mW= 47,36 W • Total : about 700 W Valérie Chambert, IPNO, 16 février 2012

  9. Power consumption for i PSA • i 2816x(15mW ampli+ADC100mW) = 325 W • Q 2816x5mW=15W • E or t PC: 9472 x5mW= 48 W • Total : about 400 W to be compared to 700 W Question : can we save PSA for Q outputs ? Valérie Chambert, IPNO, 16 février 2012

  10. ASIC for pulse shaping : IPACI, preamplifier with both current and charge outputs • Q preamplier : 2 slow control switchable ranges : - 0 to 50 MeV in Silicon - 0 to 150 MeV in Silicon • Current output gain : 7000 V/A • Resolution : 10keV tbc • Low power consumption • Integrated differential outputs Note :prototype technology AMS 0.35µm BiCMOS SiGe Valérie Chambert, IPNO, 16 février 2012

  11. Diagram for 1 channel IPACI ASIC prototype Control signals Slow control I2C or SPI Selection logic DAC_threshold 10 bits DAC 2 Gains : Q output 0/50MeV 0/150MeV threshold Fast shaper Low walk discriminator Detector input Time output Q Charge output Buffer Charge output Test input I Current output Current output Gain ×7 E. RAULY, Réunion GASPARD, IPNO, 24 octobre 2012

  12. Schedule • IPACI 1st run june/november 2013 • IPACI tests : beginning 2014 Valérie Chambert, IPNO, 16 février 2012

  13. Some pending questions • Space for embedded electronics • Cooling • Cables outputs • collaborations Valérie Chambert, IPNO, 16 février 2012

More Related