Computer Organization

1. Computer Organization

2. Basic Architecture Review • Von Neumann • Distinct single-ALU & single-Control • Fixed circuitry • Non-von Neumann • Various changes • Multiple ALUs • Merged ALU and Control • Alternatives to ALU

3. Timing • Cycle – timing in a computer comes from a master clock controlled by a crystal oscillator • Clock ticks (million cycles / sec) • Frequency = 1/period and Period = 1/frequency • Let’s use 10 MHz to make the arithmetic easier • 10 MHz = 10 x 106 Hz = 107 Hz • Period is 1 / 107 = 10-7 seconds • Terms • Giga = 109 and nano = 10-9 • Mega = 106 and micro = 10-6

4. Storage Speed Hierarchy • CPU Registers – internal to CPU • Cache (CPU Internal) – very high speed • Cache (External) – high speed • Main Memory - slow • Electronic – 0 latency • Magnetic Disks – high latency • Optical Disk – very high latency • Magnetic Tapes – seq'l, very high latency

5. Operation • Fetch – get instruction from RAM • Decode - h/w determines operation from bit pattern of first (or more) byte(s) • Obtain operand data • From Registers or RAM • Into ALU • Execute (perform the operation) • Store results back to RAM • Update Instruction Counter • (sometimes called Program Counter)

6. Device-Controller-Software Relationship S/W Application H/W API Devicecontroller Device driver Device O/S

7. Device Controller Interface • Data width • Commands • Read • Write • Seek • Status codes • Busy • Error • Done • Ready

8. I/O Operations • Controller manages device • Devices are MUCH slower than CPU • CPU can process while device runs • Need to know when done • Polling (continual testing for "done") • Special h/w for notification – interrupt flag • One bit in CPU • Turned on by device controller • Turned off by O/S • No "race" conditions

9. Interrupt Handling Sequence • Controller (atomic action) • turns on flag • Sets code indicating which device • H/W (atomic action) • Switches to privileged mode • Sets IC to interrupt handler in O/S • O/S • Interrupt handler executes • Returns to application in user mode

10. Interrupt Handler • Saves user state • IC (part of atomic ops) • Registers • Stack • Mode (kernel/user) • Switches to device-handler • Restores user's state • Returns to user with interrupts enabled • Might NOT be atomic • Allows new interrupt before switching

11. Trap or Supervisor CallInstruction • Atomic operation • Switches to privileged mode • Sets IC to common interrupt handler in O/S • Contains code for specific request • Common handler • Uses code to select address in trap table • Trap table contains addresses of specific programs

12. Instruction Processing with Interrupts No No Interruptsallowed? pending? yes fetch execute previousinst yes processinterrupt

13. Direct Memory Addressing • Allows device controller to get/put RAM w/o going through the CPU • Increases throughput • Reduces interrupt handling

14. Device addressing • Two methods shown in text: • Conventional • External to RAM • Limited only by size of address • Memory-mapped devices • Use reserved part of RAM • Limited by reserved space • Third method – used in some mainframes • Channels – addresses 00-0f (1 byte) • Sub-channels – addresses 00-ff (2nd byte) • Total of 4096 independent devices (0000-0fff)

15. Loader Processing • Find the executable file • Resolve relative addresses within program to actual locations • Connect DLL's to procedure call structure • Shared collection of programs & entry points

16. Pipelined Instructions Store Fetch Decode Execute Decode Store Fetch Execute Decode Store Fetch Execute Done Done Done

17. Software, Firmware, Hardware • Software • Programs you can install/remove/transport to another computer which are stored on disk, CD, etc and run from within RAM • Firmware • Programs usually installed only by chip maker and which run from within ROM • May be upgraded by user (depends on chip) • Hardware • The physical components of the system