1 / 15

Flipping Bits in Memory Without Accessing Them:

Flipping Bits in Memory Without Accessing Them:. DRAM Disturbance Errors. Yoongu Kim Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu. DRAM Chip. Row. Wordline. Row. Row. Row. Row. DRAM Chip. Row. Wordline. Row.

brian
Download Presentation

Flipping Bits in Memory Without Accessing Them:

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors Yoongu Kim Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu

  2. DRAM Chip Row Wordline Row Row Row Row

  3. DRAM Chip Row Wordline Row Opened Row VHIGH Row Row

  4. DRAM Chip Row Wordline Row Closed Row VLOW Row Row

  5. DRAM Chip Row Wordline Row Opened Row VHIGH Row Row

  6. DRAM Chip Row Wordline Row Opened Row VHIGH Row Row

  7. DRAM Chip Row Wordline Row Opened Row VHIGH Row Row Repeatedly opening and closing a row induces disturbance errorsin adjacent rows

  8. x86 CPU DRAM Module loop: mov (X), %eax mov (Y), %ebx clflush (X) clflush (Y) mfence jmp loop X Y

  9. x86 CPU DRAM Module loop: mov (X), %eax mov (Y), %ebx clflush (X) clflush (Y) mfence jmp loop X Y

  10. x86 CPU DRAM Module loop: mov (X), %eax mov (Y), %ebx clflush (X) clflush (Y) mfence jmp loop X Y

  11. x86 CPU DRAM Module loop: mov (X), %eax mov (Y), %ebx clflush (X) clflush (Y) mfence jmp loop X Y

  12. Most Modules At Risk 83% 88% 86%

  13. Most Modules At Risk 83% 88% 86% After After After

  14. Most Modules At Risk 83% 88% 86% After After After Errors Errors Errors

  15. Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors 4:30 PM

More Related