1 / 44

Chapter 5 Internal Memory

Chapter 5 Internal Memory. Semiconductor Memory Types. Today’s technology: 1 Gigabit / sq in In R&D: 100 Gigabits / sq in. Semiconductor Memory (SRAM). Semiconductor Memory (DRAM). 16Mbit DRAM. Semiconductor memory (EPROM). Static RAM (SRAM). Desired for main memory Used in cache

bernad
Download Presentation

Chapter 5 Internal Memory

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Chapter 5Internal Memory

  2. Semiconductor Memory Types Today’s technology: 1 Gigabit / sq in In R&D: 100 Gigabits / sq in

  3. Semiconductor Memory (SRAM)

  4. Semiconductor Memory (DRAM) 16Mbit DRAM

  5. Semiconductor memory (EPROM)

  6. Static RAM (SRAM) • Desired for main memory • Used in cache • Basically an array of flip-flops • Simple to interface and control • Fast • Relatively low density - complex • Relatively expensive

  7. Static RAM model

  8. 1K X 4 SRAM (Part Number 2114N)

  9. 1K X 4 SRAM (Part Number 2114N)

  10. 1K X 4 SRAM (Part Number 2114N)

  11. Memory Organization • A 16Mbit chip can be organised as 1M of 16 bit words • A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on • A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array • Reduces number of address pins • Multiplex row address and column address • 11 pins to address (211=2048) • Adding one more pin doubles range of values so x4 capacity

  12. Memory Design – 1K x 4 A[00:09]    D[03:00] Addr Block Select 

  13. Memory Design – 1K x 8 D[07:04] D[03:00] A[00:09]  A[00:09]    D[07:04]   D[03:00] Addr BlockSelect => Addr Block Select =>

  14. Memory Design - 2k x 8 D[07:04] D[03:00] Block 00 Block 01

  15. Memory Design - 4k x 8 D[07:04] D[03:00] Block 00 Block 01 Block 10 Block 11

  16. 22 x 3 Memory word select word WE input bits address write enable address decoder output bits

  17. 2 BIT Decoder (2 to 4)

  18. 2 to 4 Bit Decoder

  19. 3 to 8 Bit Decoder

  20. 2 to 1 MUX

  21. 4 to 1 MUX

  22. 8 to 1 MUX

  23. 16 to 1 MUX ?

  24. Register

  25. 22 x 3 Memory word select word WE input bits address write enable address decoder output bits

  26. 24 x 8 Memory ?

  27. Dynamic RAM (DRAM) • Used in main memory • Bits stored as charge in capacitors Essentially analog device Charges leak • Need refreshing even when powered Need refresh circuits • Higher density (more bits per chip) • Slower than Static RAM • Less expensive

  28. Dynamic RAM model

  29. Read Only Memory (ROM) • Permanent storage • Nonvolatile • Microprogramming (will address later) • Library subroutines • Systems programs (BIOS) • Function tables • Controllers

  30. Types of ROM • ROM: Written during manufacture • Very expensive for small runs • PROM: Programmable (once) • Needs special equipment to program • Read “mostly” • EPROM: Erasable Programmable • Erased by UV (All of chip!) • Flash memory • Whole blocks of memory stored/changed electrically • EEPROM: Electrically Erasable • Takes much longer to write than read (lower density)

  31. EPROM

  32. Semiconductor Memory 16Mbit DRAM

  33. 256kByte Module Organisation (256K x 1)

  34. Typical 16 Mb DRAM (4M x 4)

  35. 1MByte Module Organization (1Meg x 8 bits)

  36. Refreshing • Refresh circuit is included on the chip • Count through rows • Read & Write back • Chip must be disabled during refresh • Takes time • Occurs asynchronously • Slows down apparent performance

  37. Improvements in memory RAM – continually gets denser. DRAM – Several improvements: SDRAM – synchronous DRAM DDR-SDRAM - doubles transfer speed RDRAM – asynchronous one transfer per clock cycle

  38. Comparison of improved DRAM Conventional DRAM – 40 to 100 MB/S transfer rate?

  39. Synchronous DRAM (SDRAM) • Access is synchronized with an external clock • Address is presented to RAM • RAM finds data (CPU waits in conventional DRAM) • Since SDRAM moves data in time with system clock, CPU knows when data will be ready • CPU does not have to wait, it can do something else • Burst mode allows SDRAM to set up stream of data and fire it out in block • DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

  40. SDRAM Read Timing

  41. SDRAM

  42. DDR SDRAM • SDRAM can only send data once per clock • Double-data-rate SDRAM can send data twice per clock cycle • Rising edge and falling edge

  43. RAMBUS • Adopted by Intel for Pentium & Itanium • Main competitor to SDRAM • Separate bus (hence the name RAMBUS) • maximum 12 centimeter length bus ! • Bus addresses up to 320 RDRAM chips • at 1.6Gbps • Asynchronous block protocol • Precise control signal timing • 480ns access time

  44. RAMBUS Diagram

More Related