Investigation of Analog Behavioral Model
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Investigation of Analog Behavioral Model Abstractions Martin Vlach, Chief Technologist AMS, Deep Submicron Division, Mentor Graphics 8005 SW Boeckman Rd, Wilsonville, OR 97070.

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Investigation of Analog Behavioral Model Abstractions

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Investigation of analog behavioral model abstractions

Investigation of Analog Behavioral Model Abstractions

Martin Vlach, Chief Technologist AMS, Deep Submicron Division, Mentor Graphics

8005 SW Boeckman Rd, Wilsonville, OR 97070

  • Simulating analog portions of analog and mixed signal (AMS) designs at the transistor level is intractable for System on Chip (SoC) top level verification due to the length of simulation time of even the fastest SPICE-like simulations.

  • The only known alternative is to develop analog behavioral models of the analog components for use in SoC verification. It is a well known "fact" that analog behavioral modeling is "hard"; and the lack of proficiency in using analog Hardware Description Languages (HDLs) is often offered as the "proof".

  • We present a tool that can be used to develop behavioral model in a style akin to schematic capture. Models are composed graphically from effects found in libraries, and then exported to a Hardware Description Language.

  • A few notes on this approach

  • Verification experts generally agree that the behavioral model should be created by the person who knows the design best – the designer.

  • Analog designers are familiar and comfortable with composition of designs as schematics.

  • The knowledge of how to compose models that are efficient in simulation, and how to express modeling effects in an HDL is very specialized.

  • Analog and mixed-signal circuit designs are constantly evolving, and it is difficult to impossible to categorize them and create one-size-fits-all tool.

  • Engineering work is most often accomplished by the copy-and-modify methodology: new work is based on a successful previous example.

  • A few notes on the ModLyng™ behavioral modeling tool

  • The tool is built around graphical composition of models, in a manner that is familiar to the analog designer.

  • The tool allows a simulation and HDL expert to create efficient effects, thus encapsulating expert knowledge.

  • The tool treats models, effects, and testbenches identically.

  • Effects, models, and testbenches can be combined hierarchically to create other effects, models, and testbenches.

  • Libraries of effects support either continuous-time (AMS) models, or event-driven mixed-signal (aka real number) models.

Phase Locked Loop

ModLyng™ Integrated Modeling Environment

Verilog Event-Driven Mixed-Signal model preview


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