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SL-PGA firmware overview

SL-PGA firmware overview. M. Sozzi Pisa - January 30/31, 2014. Overview. Distribute clocks and timing signals to PPs Collect trigger primitives from PPs and merge them Possibly merge primitives with those from another TEL62

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SL-PGA firmware overview

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  1. SL-PGA firmware overview M. SozziPisa - January 30/31, 2014

  2. Overview • Distribute clocks and timing signals to PPs • Collect trigger primitives from PPs and merge them • Possibly merge primitives with those from another TEL62 • Pass primitives to another TEL62 or produce final sub-detector primitives • Assemble packets with multiple primitives • Distribute L0 triggers to PPs • Collect triggered data from PPs and merge them • Assemble multi-event packets • Send primitives and main data through ethernet • Handle CHOKE/ERROR lines

  3. = OK = accessible from CCPC Choke generator SL-FPGADATA ECS = In test = monitored FIFO MON Intlbtester QDR Test FIFO 1 Eventgenerator mem Eventgenerator ECS TXmem QDRinterface ECS ECS SPI3TX Checksummer MEP dataFIFO Test mem 1 Databuilder Gbit QDRmux Evt dataFIFO MON ECS ECS ECS Datapacketsender PP Eventmux MEPassembler Data headerFIFO MON ECS ECS PP-SLtester Evt lengthFIFO Headerbuilder MON ECS MEP infoFIFO ECS MEP lengthFIFO MON ECS MON ECS SPI3RX PP MON ECS Gbit PP dataFIFO RXmem Datadistributor MEPlocation mem TX hdr mem MON ECS Eventmerger ECS SL dataFIFO ECS ECS Headermem MON ECS Hdr memarbiter SL datasource TTCrx Triggerdispatcher PP TTChandler TriginfoFIFO Logger LogFIFO ChokeError QPLLmonitor Triggergenerator TypeFIFO TimestampFIFO ECS ECS

  4. = OK = accessible from CCPC SL-FPGATRIG ECS = In test = monitored FIFO Choke generator MON Primitivegenerator mem Fake primitivegenerator ECS Timestampupdater Checksummer MTP dataFIFO Test mem 1 Trigbuilder Primiitive data FIFO MTPbuffer MON ECS SPI3TX ECS ECS PP Primitivemux MTPassembler Trigpacketsender Trig headerFIFO MON ECS ECS Primitive length FIFO PP-SLtester Headerbuilder MTP infoFIFO MON ECS ECS MON MTP lengthFIFO ECS MON ECS PP MON ECS PP trigFIFO TX hdr mem Trigdistributor MON ECS Primitivemerger SL trigFIFO MON ECS SL trigsource Prev-next boards Inter TELcontroller

  5. A few random remarks • Ethernet interface is fully home-made (no IP cores used anywhere) • Jumbo frames and IP fragmentation implemented

  6. ---------- SL-FPGA Firmware version: 0x0002 Build: 0x7d1 (2001) [27/01/2014 - 17:31] Sub-detector: 0x00 [GENERIC] Source ID: 0x0 Sub-ID: 0x0 FW version: 0x01(1) Clock phases: PP0: 0x15 PP1: 0x15 PP2: 0x15 PP3: 0x15 GbE EPROM: Unprotected PP-FPGA enable: [-123] Trigger: ON TTC: ON SOB/EOB: ON Offset: 0xfc0 (100.800 us) Type timeout: 128 (3200 ns) Local trigger: OFF ECS trigger: Type: 0x00 Multi: OFF Logger: ON (L) Mask: 0x0008 Freeze manager: OFF Choke manager: 0x0f000000 Error manager: 0x00010003 Pri generator: OFF Repeat: infinite TS adjust: OFF Pri merger: OFF MTP assembler: OFF Primitives/MTP: 1 Max latency: 40.0 us TS checks: YES Trig builder: OFF Trig sender: OFF Evt generator: OFF Repeat: infinite Evt merger: ON MEP assembler: ON Events/MEP: 1 MEP/port: 1 Data builder: ON Data sender: ON Max data payload: 1472 bytes MEP/address: 1 Dynamic addresses: Trig: 0 Data: 0 TX trigger flow: OFF Ports: ---- TX data flow: ON Ports: 0--- TX GbE RX flow: OFF Ports: ---- TX memory flow: OFF Ports: ---- Words: 0 GbE TX marker: packet 0 out of 0 (128 ns duration) RX ARP flow: OFF Ports: ---- RX mirror flow: OFF Ports: ---- RX memory flow: OFF Ports: ---- slinfo

  7. ---------- SL-FPGA Mode: RUN Status: 0x001401fd Error: 0x40000200 [ TRDIS BURST ] Running since: 4244 s (435 bursts) Burst: END TS at last EOB: 0xf7fffff (6.50 s) QPLL lock: OK Lock lost: 0 ( 0.00 us) TTC: Ready TTC: Broadcast FIFO: 256 IAC FIFO: 0 Single err: 0 Double err: 0 TTC Triggers: 2989024 Timestamp: 0 [E ] Max: 1 [ ] (459.8 kHz) TTC Messages: 2989024 Trig type: 0 [E ] Max: 1 [ ] Trig dispatch: 2988999 Triginfo: 0 [E ] Max: 8 [ ] Phys: 2988997 Choke: 0 [PP: 0000 SL: 0 ] Monitor: 0 [PP: 0000 SL: 0] Count: 0 Time: 0 us Error: - [PP: 0000 SL: 0 ] Monitor: - [PP: 0000 SL: 0] ---------- TRIG FLOW ---------------------------------------------------------- Trig IB0 (PP0): 0 [E ] Max: 0 [ ] Total: 0 Trig IB1 (PP1): 0 [E ] Max: 0 [ ] Total: 0 Trig IB2 (PP2): 0 [E ] Max: 0 [ ] Total: 0 Trig IB3 (PP3): 0 [E ] Max: 0 [ ] Total: 0 Trig IB4 (SL): 0 [E ] Max: 0 [ ] Total: 0 Trig merger: Data: 0 [E ] Length: 0 [E ] Max: 0 [ ] 0 [ ] MTP assembler: Info: 0 [E ] Buffer: 0 [E ] Max: 0 [ ] 0 [ ] Primitive count: 0 MTP count: 0 MTP words count: 0 Trig builder: Header: 0 [E ] Data: 0 [E ] Length: 0 [E ] Max: 0 [ ] 0 [ ] 0 [ ] ---------- DATA FLOW ---------------------------------------------------------- Data IB0 (PP0): 0 [E ] Max: 0 [ ] Total: 0 Data IB1 (PP1): 0 [E ] Max: 301 [ ] Total: 50679083 Data IB2 (PP2): 0 [E ] Max: 324 [ ] Total: 40802477 Data IB3 (PP3): 0 [E ] Max: 35 [ ] Total: 39156406 Data IB4 (SL): 0 [E ] Max: 31 [ ] Total: 11956034 Data merger: Data: 996 [ ] Length: 0 [E ] Max: 996 [ ] 1 [ ] MEP assembler: Info: 0 [E ] Buffer: 0 [E ] Max: 3 [ ] 237 [ ] Event count: 2988998 MEP count: 2988998 MEP words count: 89293 Data builder: Header: 0 [E ] Data: 0 [E ] Length: 0 [E ] Max: 6 [ ] 14 [ ] 1 [ ] ---------- OUTPUT ------------------------------------------------------------- TX flows: Trig: 0 Data: 2988998 SPI3RX: 0 TXMEM: 0 TX ports: 0: 2988998 1: 0 2: 0 3: 0 (MB/s): 0: 78.538 1: 0.000 2: 0.000 3: 0.000 (Max): 0: 0.000 1: 0.000 2: 0.000 3: 0.000 GbE TX pause: Trig: 0 Data: 0 Time: 0 ms (0.00) Last pkt words: 53 (<= 212 bytes) slstatus

  8. ---------- GBE PORT #0 PORT #1 PORT #2 PORT #3 Link status: 1G FD UP 1G FD UP 1G FD UP 1G FD UP TX bytes OK (last): 4294967295 0 0 0 TX bytes BAD (last): 0 0 0 0 TX packets (last): 1341138100 0 0 0 RX bytes OK (last): 0 0 0 0 RX bytes BAD (last): 0 0 0 0 RX packets (last): 0 0 0 0 Autoreset watchdog: NO Frame sync: OK DLL: OK PLL: OK Bunch counter: 540 Event counter: 125984 Single errors: 0 Double errors: 0 SEU errors: 0 gbestatus ttcrxstatus

  9. Data format

  10. Missing/coming • Trigger primitive transmission at periodic interval • Self-triggering mode using (lowest 8bit of) generated primitives • Inter-TEL communication (and primitive merging) • Ping implementation • More error protection (e.g. QDR overflow) • More error handling/recovery • Proper handling of all special triggers • Full propagation of backpressure (to CHOKE) • Removal of asynchronous resets, completion of error persistence • High-statistics internal tests

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