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DOR Firmware

DOR Firmware. A Short Overview K.-H. Sulanke DESY Zeuthen. Contents. Firmware Versions Main Features Status Open Issues . Three Firmware Versions. DOR_TEST: After production test No tricky state machines, but access to every bit and byte DCOM_TEST:

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DOR Firmware

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  1. DOR Firmware A Short Overview K.-H. Sulanke DESY Zeuthen K.-H. Sulanke

  2. Contents • Firmware Versions • Main Features • Status • Open Issues K.-H. Sulanke

  3. Three Firmware Versions • DOR_TEST: • After production test • No tricky state machines, but access to every bit and byte • DCOM_TEST: • To check the fast communication in loop back mode (wire pair #0<->#2, #1<->#3) • Two virtual DOMs are connected to wire pairs 2,3 • Special debugging registers • DOR, Rev. 1.4 : • Working version, presently under development • All versions base on 32 x 32 bit registers • Can be mapped into I/O or memory space • Firmware revision register available K.-H. Sulanke

  4. Data Buffer SRAM 2 x 256Kx16 P C I - C o r e DOM 1..4 PCI Bus Altera FPGAEP20K200E DOM 5..8 Config JTAG JTAG JTAG Altera PLD EPM7064 FLASH 1M x 8 Clock 96 V Cable Interface #3 Cable Interface #2 Cable Interface #1 Cable Interface #4 DOR, Block Diagram 2 2 2 2 Reload K.-H. Sulanke

  5. FPGA Loading from FLASH small PLD: state machine, timer and address counter reads the FLASH page #0 and loads the FPGA after power on, PC reset button or software initiated K.-H. Sulanke

  6. DOR Firmware, Rev. 1.4, Main Features K.-H. Sulanke

  7. External Buffer • Presently the FPGA internal buffer and is used only • Per DOM 512 byte Tx FIFO, 2KB Rx FIFO • for Rx > 4 KB would be better (software related) • Wire pair #0,#1 (4 DOMs) supported • External 1MB SRAM, organized 2 x 256Kx16 • Every DOM gets 128KB buffer (8KB Tx, 128KB Rx ?) • Maximum data throughput from the cable side is 200KB/s x 4 ~1MB/s • At the PCI Bus side, ..132MB/s, 80MB/s realistic with DMA • This ratio allows to share the SRAM (2 chips) with the PCI Bus access and up to 4 DOMs • The data transfer from the DOM cannot be stopped within a packet • Idea is to use a fixed scheduler plus small intermediate buffers K.-H. Sulanke

  8. Time Calibration • Initiated either by software or by a programmable timer • Completely under hardware control • Transparent for normal DOM data taking • The round trip measurement takes about 1 ms / DOM • 4x8 byte time stamp + 32 ADC bytes = 64bytes * 10μs = 640 μs • 640 + 35μs (cable delay) +… < 1ms • Could be worse, if additional cable quiet time is needed • Within a quad only one TCAL at the same time • 4% bandwidth loss, if TCAL every 100ms • DOR firmware writes a packet with a TCAL-header to the Rx FIFO K.-H. Sulanke

  9. Next Steps • TCAL • External buffer control • Fast communication improvements • DOM current measurement + electronic fuse K.-H. Sulanke

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