Soc architecture course oct 2008 jan 2009 kth
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SoC Architecture Course Oct 2008 – Jan 2009, KTH. Zhonghai Lu / Axel Jantsch [email protected] Course Information. Course responsible: Dr. Zhonghai Lu Course examiner: Prof. Axel Jantsch 12 Lectures, 4 Tutorials, 3 Labs Home page: www.ict.kth.se/courses/IL2207 Course Material

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SoC Architecture Course Oct 2008 – Jan 2009, KTH

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Soc architecture course oct 2008 jan 2009 kth

SoC Architecture CourseOct 2008 – Jan 2009, KTH

Zhonghai Lu / Axel Jantsch

[email protected]


Course information

Course Information

  • Course responsible: Dr. Zhonghai Lu

  • Course examiner: Prof. Axel Jantsch

  • 12 Lectures, 4 Tutorials, 3 Labs

  • Home page: www.ict.kth.se/courses/IL2207

  • Course Material

    • Dally, Towles: Principles and Practices of Interconnection Networks

    • Distributed Material

    • Slides

  • Advanced-level course, more demanding

SoC Architecture


Lecture overview

Lecture Overview

  • L1: Introduction

  • L2: Buses and Arbitration (Dally: 22, 18)

  • L3: Shared Memory Multiprocessors

  • L4: Cache Coherency Protocols

  • L5: Memory Consistency

  • L6: Introduction to Network-on-Chip, Topologies (Dally: 1, 2, 3, 4, 5)

  • L7: Routing Algorithms and Mechanics (Dally: 8, 9, 10, 11)

  • L8: Flow Control (Dally: 12, 13)

  • L9: Deadlock and Livelock (Dally: 12, 13, 14)

  • L10: Router Architecture and Network Interface (Dally: 16, 17, 20)

  • L11: Quality of Service and Performance Analysis (Dally: 15)

  • L12: Course Summary and Trends

SoC Architecture


Tutorial overview

Tutorial Overview

  • T1: Bus, arbitration and cache coherency

    • After Lecture 5, on Nov. 5

    • By Prof. Jantsch 

  • T2: Memory consistency and network topology

    • After Lecture 7, on Nov. 12

    • By Dr. Lu

  • T3: Interconnection networks (routing, flow control, deadlock etc.)

    • After Lecture 8, on Nov. 19

    • By Dr. Lu

  • T4: Router architecture, QoS and performance analysis

    • After Lecture 12, on Dec. 3.

    • By Prof. Jantsch

SoC Architecture


Lab overview

Lab Overview

  • Laboratory 1: Uniprocessor SoC Design with Altera

  • Laboratory 2: Multiprocessor SoC Design with Altera

  • Laboratory 3: Wormhole Networks

  • Students work in groups of max. 2

  • Good preparation is required.

SoC Architecture


Course requirements

Course Requirements

To pass the course the student has to fulfill the following requirements:

  • Pass the final exam. The grade for the exam will be the grade of the course.

    • Final exam: Dec. 16, 2008, 9:00-13:00,

      Room 432, 438, 439,530

    • ** Register the exam in Daisy 2 weeks before the exam date in order to guaranttee a seat *!

  • Attend tutorials

  • Complete all labs

SoC Architecture


Observations in system design

Observations in System Design


Advances in integration

Intel 4004

(1971)

108 KHz

2,300 transistors

If automobile speed had increased similarly over the same period, we could now drive from Stockholm to Shanghai in about 23 seconds.

Advances in Integration

Intel Pentium 4

(2000)

1.5 GHz

42 million transitors

SoC Architecture


Advances in integration 2007

Advances in Integration - 2007

  • Intel Terflop Chip 2007

  • http://techresearch.intel.com/articles/Tera-Scale/1449.htm


Growing design productivity gap

Moore’s Law:

Standard cell density and speed

Design Productivity Crisis

Potential Design Complexity and Designer Productivity

10,000

10,000

100,000,000

Equivalent Added Complexity

1,000

10,000

Logic Tr./Chip

58%/yr compounded

Complexity Growth Rate

Tr./S.M.

1,000

100

100

10

1,000

Density (Kgates/mm2)ASIC clock (MHz)

Logic Transistor per Chip (M)

10

1

Productivity (K) Trans./Staff – Mo.

21%/yr compounded

Productivity Growth Rate

x

x

1

0.1

x

x

x

x

x

x

Gates

0.1

0.01

Clock

0.01

0.001

100

2009

2013

2001

2003

2005

2007

2011

2015

1985

1989

1987

1983

1991

1993

2009

1981

1995

1997

2007

1999

2001

2003

2005

Source: (SRC 1997)

Growing Design-Productivity Gap

Designs do not only get more complex, but also much more expensive!

SoC Architecture


The role of the market

The Role of the Market!

Source: Smith 1997

SoC Architecture


Moore s law drives the development of system in chip architectures

RTL

function 1

Processor

RTL

function 2

RTL

function 3

Yesterday’s SOC

Memory

RTL

I/O

RTL

RTL

RTL

Ctl

Proc

RTL

RTL

RTL

RTL

RTL

Today’s SOC

RTL

Mem

RTL

RTL

RTL

RTL

RTL

DSP

RTL

I/O

RTL

RTL

Mem

Moore’s Law drives the development of System-in-Chip Architectures

The growing number of transistors on an SOC drives the trend towards more RTL blocks on the chip

Source: Leibson (DAC2004)

SoC Architecture


Verification costs

Verification Costs

  • The percentage of the verification costs of the total design costs is continuously increasing (at present 50-70% for large designs)

SoC Architecture


Platforms reduce costs

Platforms reduce Costs

SOC Flexibility = Per-Unit Cost Reduction

(Model: 100K and 1M system volumes)

Source: Leibson 2004

Low-endstill camera

High-endstill camera

Total per unit cost

Video camcorder

System designs per chip design

One Chip

Many System Designs

$10M design cost, $15 manf. cost, 5% premium for programmability

SoC Architecture


Platform example nexperia

Platform Example: Nexperia

SoC Architecture


Nexperia instance viper

Nexperia Instance: Viper

SoC Architecture


Arm based mpsoc platform

Arm based MPSoC Platform

SoC Architecture


Texas instruments omap a soc platform

Texas Instruments OMAPA SOC Platform

based on

Peter Cumming: ”The TI OMAP Platform Approach to SOC”


The omap platform

The OMAP platform

  • OMAP products are combinations of hardware and software allowing mutimedia capabilities to be included in 2.5G and 3G wireless handsets and PDAs

  • Critical design paramters are: Performance, Power, Cost and Time-to-Market

  • First Approach: ”Opportunistic Reuse”

    • No planned reuse, but try to reuse whenever possible

  • Second Approach: ”Structured Approach”

    • Systematic Reuse, SoC Platform

SoC Architecture


What is a platform

What is a platform?

  • OMAP defines a platform as

    • ”a packaged capability used in subsequent stages of the development to reduce development costs”

  • Platforms have the following characteristics:

    • Between silicon and systems many platforms may be developed and used in subsequent stages of the development

    • Platforms are valuable due to the notion of reuse (good for economy)

    • They include hardware, software, assemblies and tools!

SoC Architecture


Examples for platforms

Examples for platforms

  • Transistor and ASIC libraries are the lowest hardware platforms

  • Instruction Set Architecture and associated Assembly Language Tools are the lowest levels in Software

  • These well-understood levels are used by other OMAP platforms

SoC Architecture


Omap hierarchy of platforms

OMAP: Hierarchy of Platforms

  • OMAP uses platforms on different levels

  • This is a precondition for reuse

Application

Specific

Ref

Design

Appl.

Platform

OMAP Products

OMAP Infrastructure

SoC Platform

ASIC Library & Tools

Reuse

Silicon Technology

SoC Architecture


Soc platform

SoC Platform

  • The SoC platform consists of

    • A library of hardware components

    • An architecture for their interconnection

  • The Application Platform (the OMAP product)

    • Processor and Peripherals

    • Low-Level Software (Drivers)

    • Development Environment

  • The System Platform

    • The platform includes the code that controls all aspects of the system from device driver to system interface

    • TI has a reference design group in order to understand the new demands for OMAP

SoC Architecture


Omap products

OMAP Products

  • The OMAP product range consists of several families of devices for different markets, e.g.

    • Application processors for 3G: OMAP 1510 and 1610

    • Application processors for 2.5G: OMAP 710 and 730

SoC Architecture


Omap 1510

OMAP 1510

  • OMAP 1510 is based on

    • Enhanced ARM 925 core (RISC processor)

    • TI C55x core

    • DMA, SRAM, Busses, Peripherals

SoC Architecture


Current omap platform for wireless handset pda

Current OMAP platform for Wireless Handset & PDA

  • OMAP™ 3 architecture combines mobile entertainment with high performance productivity applications (Source: Texas Instruments)

SoC Architecture


Strength of the omap concept

Strength of the OMAP concept

  • The main strength of the OMAP concept is that several actors can make extensive Reuse of development efforts at several levels of the design process

  • Actors:

    • Mobile Device Manufacturers

    • Software Developers

    • TI’s internal Development Teams

  • Levels:

    • Common Hardware and Software Interfaces

    • Common Development Environment

    • Single Low-Level Software Framework (Code can be used for several products)

    • Single SoC Platform

  • OMAPI is an interface standard for OMAP founded by TI and ST

SoC Architecture


Oamp architecture

OAMP Architecture

  • The OMAP architectute consisting of general purpose processor and DSP has been chosen because of the application area

    • Need for Performance

    • Energy and Area Constraints

    • Two Main Tasks: User Interface and Signal Processing

    • Flexibility and Reuse

SoC Architecture


Requirements on software platform

Requirements on Software Platform

  • Hardware architecture requires a matching software approach

    • Well-defined Set of Application Programming Interfaces in the high-level OS running on the general purpose processor

    • System Software that links General Purpose Applications to DSP components

    • Well-defined Standard for DSP Components (TMS320 Algorithm Standard or eXpressDSP)

SoC Architecture


Summary

Summary

  • The OMAP platform

    • Covers a wide range of products allowing to reuse Hardware and Software

    • Hardware Architecture adopted to Application Area

    • Software Architecture using features of Hardware Architecture

    • Efficient SOC Platform with Definitions for Hardware and Software Reuse

SoC Architecture


Emerging architectures

Emerging Architectures


System on chip architectures

Memory

FPGA

Micro-

controller

Analog-

Digital

Digital-

Analog

Communication

Structure

Custom

Hardware

DSP

System-on-Chip Architectures

  • A system-on-chip architecture integrates several heterogeneous components on a single chip

  • A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead

SoC Architecture


System on chip architecture a bus based soc

Memory

Micro-

processor

DSP

Custom

Logic

I/O

System-on-Chip Architecture:A bus-based SoC

System on a chip

SoC Architecture


System on chip architecture network on chip

System-on-Chip Architecture: Network-on-Chip

Switch

  • The resources are connected to the network via network interfaces

  • The topology of the network and the capability of the switches and communication channels determines the capacity of the network

PE3

PE1

NI

NI

Resource

Channel

PE2

MEM

NI

NI

Network Interface

SoC Architecture


Asic technologies

ASIC Technologies


What is an asic

What is an ASIC?

  • ASIC = Application Specific Integrated Circuit

  • An ASIC is an integrated circuit for a specifc application and (generally) produced in relatively small volumes.

  • An ASIC-technology helps to shorten the design time by providing a semi-fabricated integrated circuit

SoC Architecture


Asic families

Programmable Logic

Programmable Logic Device (PLD)

Field Programmable Gate Array

ASIC

Standard Cell

Gate Array

ASIC families

The term ASIC is often reserved for circuits that are fabricated in a silicon foundry, while circuits that can be programmed at the customer’s site are called Programmable Logic.

The term full custom is reserved for circuits where all silicon layers can be optimized. This implies a long design process and thus full custom is mainly used for high-volume high-end circuits.

SoC Architecture


Standard cell

Standard Cell

  • Standard cells are often referred as Cell-Based Integrated Circuits (CBIC)

  • All mask layers are customized

  • The standard cell library defines logic elements of varying complexity: SSI, MSI logic, data path blocks, memories and system-level blocks.

SoC Architecture


Standard cells

Standard Cells

  • Cells are configured in rows and have constant height and variable width

  • Each cell is optimized for an efficient implementation

SoC Architecture


Gate array

Gate Array

  • A gate array chip contains prefabricated adjacent rows of PMOS and NMOS transistors

  • The gate array is configured by the interconnect structure

SoC Architecture


Channeled gate array

Channeled Gate Array

  • Only the interconnect is customized

  • The interconnect uses spaces between rows of base cells

SoC Architecture


Channelless gate array sea of gates

Channelless Gate Array(Sea of Gates)

  • Only the interconnect is customized

  • Cells are connected via unused transistors

SoC Architecture


Field programmable gate arrays

Field Programmable Gate Arrays

  • None of the layers are customized

  • Basic logic cells and interconnect can be programmed

  • Basic cells can be SRAM based, Flash Memory based or fuse-based (one time programmable)

SoC Architecture


Programmable logic device

Programmable Logic Device

  • No customized mask layers or logic cells

  • A single large block of interconnects

  • Macrocells consist of programmable array logic followed by a flip-flop or latch

SoC Architecture


Comparison fpga gate array standard cell

Comparison FPGA, Gate Array, Standard Cell

SoC Architecture


Design trade offs

Design Trade-Offs

Design Time

Full Custom

Standard Cell

Gate Array

Programmable

Logic

Microprocessor

Performance

SoC Architecture


Challenges for system design

Challenges for System Design


How to design a system on chip

Design

Product (Implementation)

How to design a system-on-chip?

Idea (Specification)

  • Specification

    • Design productivity increases with the level of abstraction

    • The task of functional verification is very difficult at low abstraction levels

abstract

Abstraction Gap

  • Implementation

    • Efficient implementations require to exploit the low-level features of the target architecture

detailed

Challenge for

System Design!

SoC Architecture


Soc design

SoC Design

  • The continuous progress in silicon process technology allows to increase more and more functionality on a single chip => Systems on a chip become reality

  • Market-driven forces:

    • Shorter product design schedules and life spans

    • Products have to confirm to standards

    • The design has to be right from the start. An implementation error means heavy loss of money or product death

    • Large designs are integrated into a single chip

The SoC design process must address these driving forces

SoC Architecture


The design process

Design Step

Abstraction Gap

Intermediate Model

Design Space

The Design Process

Design Specification

Abstraction Level

Implementation

SoC Architecture


Requirements on design flow

Requirements on Design Flow

  • Design Entry

    • Well-defined abstract specification model

    • Efficient verification methodology

  • Design Refinement

    • Well-defined models at all abstraction levels

    • Well-defined refinement steps

    • Verification at all levels

SoC Architecture


Requirements on design flow1

Requirements on Design Flow

  • Implementation Mapping

    • Efficient platform architecture with well-defined API

    • Mapping detailed implementation model to API services

  • Tool Support

    • Verification

    • Design Refinement

    • Implementation Mapping

    • Estimation of Properties

SoC Architecture


Design process

A design specification has to be mapped on an architecture

Design Process

Design

Specification

Architecture

Specification

Design

Process

Design

Implementation

SoC Architecture


Design process uniprocessor

A program is compiled to assembler code for a chosen uniprocessor and operative system

Design Process(Uniprocessor)

Program

(Parallel Tasks)

Uniprocessor

+

Operating Syst.

Compilation

Executable

Code

SoC Architecture


Design process1

Design Process

  • The design process for a SoC applications is a very complex task

    • Many components work in parallel and communicate with each other

    • A task can be mapped on different components

    • The overhead for communication depends on how tasks are located

    • The designer has to choose an appropriate SoC architecture, since different architectures have different strength and weaknesses

SoC Architecture


Design process system on chip

A specification shall be mapped onto a SOC-Architecture with several heterogeneous components

Design Process(System-On-Chip)

Specification

(Parallel Tasks)

SoC Arch.

with several

components

Partitioning, Mapping,

Compilation

HW Descr.

Comp. A

Code

Processor X

HW Descr.

Comp. B

Code

Processor Y

SoC Architecture


Platform based design

Programmers Model

Hardware Abstraction

Hardware Platform

FPGA

Memory

Micro-

controller

Communication

Structure

Analog-

Digital

Digital-

Analog

DSP

Custom

Hardware

Platform-Based Design

The idea of a platform is to simplify the design process

SoC Architecture


System on chip platform

API

Services with Guarantees

Transaction

Messages, Load/Store

Transport

Packets

Physical

Wires, Clocks

System-on-Chip Platform

  • Layered Concept allows to

    • Change the physical architecture of the SoC without affecting the application

    • Add new services on top of existing architecture

  • Changes in one layer affect only the layer itself and its interfaces

SoC Architecture


Concurrency

Concurrency


Embedded systems have to cope with parallelism

Sink

C

A

Embedded

System

Reactive Environment

D

B

Source

Embedded Systems have to cope with Parallelism

  • Provides an alternative to faster clock for performance

  • Applies at all levels of system design

  • Is essential within embedded system design, where the system has to react to several inputs from the environment

SoC Architecture


System on chip a parallel architectures

System-on-Chip:A Parallel Architectures

  • A parallel computer is a collection of processing elements that cooperate to solve large problems fast

    • Resources

      • Processing capacity of the components

      • Distributed and/or global memory

    • Data access, Communication and Synchronization

      • Communication protocol

      • Communication capacity

      • Communication abstraction and primitives

  • Objectives

    • Performance and Scalability

SoC Architecture


Components in a parallel soc

Components in a Parallel SoC

  • Microprocessor cores or DSP:s are cheap and optimized for their application area

  • Customizable hardware can be used to guarantee a high performance for a special task

  • Often each parallel task does not need a tremendous processing power

  • It is important, how the parallel tasks can be mapped onto the SoC so that the parallel nature of the system can be fully exploited

SoC Architecture


Communication primitives system on chip

Communication PrimitivesSystem on Chip

  • There are two main paradigms

    • Shared Memory

    • Message Passing

SoC Architecture


Communication primitives system on chip1

Memory

Micro-

processor

DSP

Custom

Logic

(ASIC)

I/O

System on a chip

Communication PrimitivesSystem on Chip

  • Shared memory is typical for bus-systems, since naturally a memory is connected to the bus that all processing entities can access

SoC Architecture


Communication primitives network on chip

Switch

PE3

PE1

NI

NI

Channel

PE2

MEM

NI

NI

Network Interface

Communication PrimitivesNetwork on Chip

  • Message passing looks very natural for networks-on-chip, since a shared memory is usually not available

  • However, locality is important, since otherwise huge amounts of data have to be sent over a network

SoC Architecture


Message passing

Message Passing

Message

  • Processes send messages between processes

  • A message has a sender and and receiver(s)

  • Primitives are Send and Receive

  • Programming does not include a shared memory

P1

P2

SoC Architecture


Programming model for message passing

Programming Model for Message Passing

  • Natural Model for NoCs: Communicating Finite State Machines

  • Communication is done by message passing (languages like SDL are suitable)

A

C

Process

Receive Message

(Wait for message)

Send

Message

D

B

SoC Architecture


Implementation of a message passing programming model

Implementation of a Message Passing Programming Model

  • A programming model based on message passing can still be implemented by a shared memory architecture

  • Each layer has to use the primitives that are provided by their lower layer neighbour

Source Code

uses High-Level Comm. Primitives

Compiled Program

uses Low-Level Comm. Primitives

Operating System

uses Hardware Drivers

Mem

P1

P2

here Shared Memory Comm.

(can also be NoC)

Hardware

SoC Architecture


Summary1

Summary

  • System-on-Chips are heterogeneous and parallel

  • A good communication is the key to an efficient parallel architecture

  • In the course we will mainly focus on comunnication architectures

    • Buses

    • Network-on-chip

SoC Architecture


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