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CRKIT R5 Architecture rev 0.1

CRKIT R5 Architecture rev 0.1. WINLAB – Rutgers University April 25, 2013 Khanh Le. R5 Architecture Summary. Objective : migration of R4 to Zynq platform + support of new RF module (400MHz-4GHz tuning range)

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CRKIT R5 Architecture rev 0.1

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  1. CRKIT R5 Architecturerev 0.1 WINLAB – Rutgers University April 25, 2013 Khanh Le

  2. R5 Architecture Summary • Objective : migration of R4 to Zynq platform + support of new RF module (400MHz-4GHz tuning range) • Zynq : Integrated dual-core ARM processor + peripherals e.g. GigE, USB, i2c, SPI, UART… • What are the Hardware implications ? • Access to GigE port through AMBA AXI bus -> new Ethernet port module (ethernet framing by PS) • New RF ports e.g. DA/AD interface modules • New PCORE wrapper containing ARM processor and dual AXI busses • New AXI ipif modules for AXI bus interfacing : one for RMAP Processor, one for Ethernet port • Replace SPI with I2C interface. Current SPI is no longer needed (remove). I2C is provided by PS. • Potentially replace all R4 FIFOs and Block RAMs • New clock architecture • What are the Software implications ? • Add DMA support for PS GigE -> PL Ethernet Port • Add DMA support for PL Ethernet Port -> PS GigE • Some changes to overall memory map due to dual AXI bus architecture • Changes to RF control due to I2C interface and new radio (refer to ADI reference design) • APP design remains the same, only Xilinx IPs may need to be replaced due to tool revision updates • Overall software remain the same, no Linux support for the initial phase. • Once HW is stable, port Linux including VITA support. • Target design methodology : mixed-language, C/SystemC, UVM • Goal for DARPA Challenge : functional spectrum sensing APP (mid-august time frame)

  3. Implications to R4 Architecture Serial IO + ref. clock modifications Modify access thru AXI bus SPI no longer applicable. Replace with I2C interface Replace PLB IPIF with AXI IPIF Replace with ARM core, contains dual AMBA AXI busses : AXI0 -> GbE, AXI1 -> Framework

  4. Zynq System-on-Chip Overview CPU Cores Programmable Peripherals : UART, I2C, GigE Processor subsystem (PS) Fixed external IO pins Programmable Logic (PL) AXI Master/Slave Ports Refer to Xilinx user guide ug585-Zynq-7000-TRM.pdf for further details

  5. CRKIT Framework Integration CRKIT PCORE RMAP Processor AXI0 – 32-bit, Master Port AXI1 – 32-bit, Master Port AXI1 AXI IPIF 0x8000_0000 0xBFFF_FFFF AXI0 0x4000_0000 0x7FFF_FFFF RF GbE AXI IPIF APP + PKT

  6. PS <-> IPIF data paths PCORE PS PL PL PL BUS2IP M_AXI_GP0 M S M S M M S IP2BUS 0x4000_0000 0x7FFF_FFFF system_axi_interconnect_0_wrapper (axi bus 0) system_axi_ext_slave_conn_0_wrapper (external connector 0) axi_ipif_slv (gbe) PL PL PL BUS2IP M_AXI_GP1 M S M S M M S IP2BUS 0x8000_0000 0xBFFF_FFFF system_processing_system7_0_wrapper (processor) system_axi_interconnect_1_wrapper (axi bus 1) system_axi_ext_slave_conn_1_wrapper (external connector 1) axi_ipif_slv ( rmap processor) Bring internal AXI signals to top level

  7. R4 - host2app PCORE CMD FORMAT Ethertype = 0x0800 - IPv4 0x0806 - ARP If (V==1) then VITA context packet Else non-VITA packet use ethertype field for further parsing Endif; Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM. REPLACE • Forward ethernet payload if : • incoming MAC = dMAC • incoming MAC = Broadcast • Append Ethertype field (16-bit) to ethernet payload if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver else forward packet to PCORE

  8. GbE -> IP Data Path (Option 1) • MAC filtering • Jumbo frames not supported 2. DMA done GbE ARM Cortex A9 1. DMA xfer 3. Generate CMD Processor Subsystem DMA AXI BUS 0 Complete ETH packet storage (circular buffer) Skip ETH header, Prepend Ethertype field to payload DP RAM PKT CTL Elastic Buffer CRKIT Framework AXI SLAVE IPIF Ethertype field + IP packet CMD FIFO GbE Rx (R5) Packet Processor (R4) 31 29 15 0 - size[13:0] ptr[15:0] Fixed length buffer size allocation e.g. min. 1600 bytes -> 400 words (may depend of DP RAM size -> end on a full buffer boundary)

  9. GbE -> IP Data Path (Option 2, no processor assistance) • MAC filtering • Jumbo frames not supported 2. DMA done GbE ARM Cortex A9 1. DMA xfer Processor Subsystem DMA AXI BUS 0 Complete ETH packet storage (circular buffer) Skip ETH header, Prepend Ethertype field to payload DP RAM PKT CTL Elastic Buffer CRKIT Framework AXI SLAVE IPIF CMD GEN Ethertype field + IP packet CMD FIFO Snoop on bus Interface to generate CMDs (write only). GbE Rx (R5) Packet Processor (R4) 31 29 15 0 - size[13:0] ptr[15:0] Fixed length buffer size allocation e.g. min. 1600 bytes -> 400 words (may depend of DP RAM size -> end on a full buffer boundary)

  10. GbE -> IP Data & Control Flows 8-byte descriptor 1600-byte buffer 7. +Search for used descriptor e.g. ownership flag == 1 +clear ownership flag (allows descriptor to be reused by GbE DMA ctl.) ARM Cortex A9 6. DMA done intr GbE 2. +Init DMA controller +init ptr to RBD entries +enable GbE receiver (refer to programming guide, ug585, pg. 436) 1. Init Rx Buffer Descriptors (RBD) (refer to ug585, pg. 418) GbE 3. Fetch descriptor (ptr to BRAM) OCM BRAM On-chip Memory 256KB DMA 5. Update xfer control stat Assuming available rx packet 16 RBD entries e.g. 32 words 4. DMA xfer Enable Receiver : gem.net_ctrl[rx_en] == 1 BRAM Refer to ug585, Programming guide, page 436 for additional details.

  11. Rx Buffer Descriptor Entry Pointer to Rx DPRAM buffer Ownership flag Reference : ug585, page 418

  12. R4 - app2host if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP) else Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP) endif Lookup using PortID dMAC/Ethertype from IP Processor VRT Receiver REPLACE Lookup using PortID dMAC/Ethertype appended to IP/VITA data if (V == 1) then Enable VITA formatting else Disable VITA formatting endif

  13. IP -> GbE Data Path +Jumbo frames not supported + append FCS field (enabled at Tx Buffer Descriptor) 4. Setup DMA GbE ARM Cortex A9 5. DMA xfer 2. Fetch CMD Processor Subsystem DMA 1. Intr AXI BUS 0 Generate complete Ethernet header e.g. dMAC, sMAC, ethertype/size. FCS added by PS GbE MAC Fixed length buffer allocation CTL REG sMAC DP RAM ETH HDR GEN Elastic Buffer CRKIT Framework AXI SLAVE IPIF CMD GEN CMD FIFO dMAC + Ethertype + IP packet INT REG GbE Tx (R5) Packet Processor (R4) 31 29 15 0 - size[13:0] ptr[15:0] Fixed length buffer size allocation e.g. min. 1600 bytes -> 400 words (may depend of DP RAM size -> end on a full buffer boundary)

  14. IP -> GbE Data & Control Flows 9. clear all status bits, including used flag (optional) ARM Cortex A9 8. DMA done intr (optional) 4. Set Transmit_Start bit e.g. bit-9 of Network Control register) (ug585, pg. 436) 3. +setup Tx Buffer Descriptors (TBD) +clear used flag (refer to ug585, pg. 423) GbE 5. Fetch descriptor (ptr to ETH packet) On-chip Memory 256KB DMA 7. Update xfer control stat (set used flag to ‘1’) 1 TBD entry e.g. 2 words 1. intr 2. Fetch CMD size + ptr 6. DMA xfer Init. + enable Tx DMA engine ( gem.net_ctrl[tx_en] == 1) CRKIT GbE Tx Refer to ug585, Programming guide, page 436 for additional details. Assuming available tx packet

  15. Tx Buffer Descriptor Entry Pointer to Tx Buffer used flag wrap flag Reference : ug585, page 423 Set to 1 for single buffer

  16. DA Port

  17. AD Port

  18. Clock architecture

  19. Memory Map

  20. R4 - PCORE PCORE – RMAP RD/WR IP Host -> PCORE (UDP-1001) RTYPE: 0x2000 – RMAP READ 0x2001 – RMAP WRITE RADDR: Register address RDATA: Register data Address Decoding IP PCORE -> Host (UDP-1001)

  21. R4 - APP

  22. R4 – Memory Map Upper 4 MSBs : 0x0-0x1 : PCORE 0x2 : CRKIT Others : Unused 0x0 : CMN 0x1 : ETH 0x2 : PKT 0x4-0xB : APP 0xC : DAC IF 0xD : ADC IF INT SPI, LED DCM/CLOCK CE

  23. R4 – Interrupt Architecture CMN INT ETH INT PKT INT uP INTC IPIF APP INT SYS INT PCORE CR

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