Crkit r5 clock architecture
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CRKIT R5 Clock Architecture. WINLAB – Rutgers University June 13, 2013 Khanh Le. Zedboard Zynq System Clock Overview. 4 programmable PLL clocks. E19, E20. dac_clk_out (dac source synchronous clock). PS. PL. L18, L19. dac_clk_in (dac ref clock). 33.333MHz ref clock (IC18, PS_CLK).

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CRKIT R5 Clock Architecture

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Crkit r5 clock architecture

CRKIT R5Clock Architecture

WINLAB – Rutgers University

June 13, 2013

Khanh Le


Zedboard zynq system clock overview

Zedboard Zynq System Clock Overview

4 programmable

PLL clocks

E19, E20

dac_clk_out (dac source synchronous clock)

PS

PL

L18, L19

dac_clk_in (dac ref clock)

33.333MHz

ref clock

(IC18, PS_CLK)

F7

B19, B20

ref_clk_out (RF ref clock ~30MHz)

D18, C19

adc_clk_in (adc source synchronous clock)

Y9

For portability, use the 100MHz reference clock for PL section

(will require one PLL)

100MHz

ref clock

(IC17, GCLK)


Zynq ps system clocks

Zynq PS System Clocks

Clock

Ratio

Generator

CPU, SCU

OCM

cpu_6x4x

ARM PLL

cpu_3x2x

6-bit prog.

divider

Mux

Sync

AXI

Interconnect

cpu_2x

33.333MHz

PS_CLK

I/O PLL

cpu_1x

DDR PLL

6-bit prog.

divider

ddr_3x

Async

6-bit prog.

divider

ddr_2x

Async

Check the clocks

on EDK tool !!

I/O Peripherals

USB, Ethernet

SDIO, SMC

6-bit prog.

divider

Mux

SPI, QSPI, UART

CAN, I2C

PL

PL Clocks


Rf interface

RF Interface

LVDS

dac_data_out[15:0]

AD9122

DAC

I

Q

dac_clk_out

ODDR

dac_frame_out (unused)

1

0

Not used for word-level, only for

Byte- or Nibble-level

AD9523

Clock Gen

dac_clk_in

clock feedback

tx_sys_clk

CMT

PLL

AD9548

Clock Sync

DAC Interface

ref_clk_out(~30MHz)

Jitter clean up

RF Reference Clock

adc_data_in[13:0]

AD9643

ADC

adc_clk_in

adc_or_in

ADC Interface

I2C Interface


Dac clock

DAC Clock


Ad port

AD Port


Clock architecture

Clock architecture


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