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Selected information on Altera FPGAs and Software

They have very good University program Donated 4 boards to PSU for free Help with projects. Selected information on Altera FPGAs and Software. European Technical Center High Wycombe, U.K. IC, Software & IP Design Focus on Telecommunications Asian Technical Center Penang, Malaysia

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Selected information on Altera FPGAs and Software

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  1. They have very good University program Donated 4 boards to PSU for free Help with projects Selected information on Altera FPGAs and Software

  2. European Technical Center High Wycombe, U.K. IC, Software & IP Design Focus on Telecommunications Asian Technical Center Penang, Malaysia IC Design and Test Engineering 62,000 Sq. Foot Facility Supports up to 350 Employees Additional R & D Centers Santa Cruz CA, USA Ottawa, Canada Toronto, Canada ABOUT THE COMPANY Worldwide Research & Development Altera Asian Technical Center Penang, Malaysia

  3. World-Class Wafer Foundries Sharp & TSMC Multiple Foundries in Asiaand North America Ensures Supply Continuity State-of-the-Art Development Partnership with TSMC 0.42-µ, 0.30-µ, 0.22-µ and 0.18-µ Processes Released to Production 0.15-µ and 0.13-µ Processes with Copper Interconnect 12 inch Wafer Development Underway Worldwide Manufacturing Capacity

  4. Altera Offices

  5. Revenue by Channel Europe 22% Japan 15% North America 57% Asia-Pacific 6% 2000 Total $1.38B

  6. Revenue by Market Segment EDP 17% Industrial 11% Communications 67% Consumer 2% Other 3% 2000 Total $1.38B

  7. Altera Communications Solutions All Areas of Communications • Telecom • Networking • Mobile Communications • Broadcast & Studio

  8. Price Trend 1.2 1 1 Price per Logic Element (LE) 30% to 40% Lower per Year 0.901 0.8 0.6 Price per LE Sold (Normalized to Q1 1993) 0.578 0.4 0.354 0.261 0.17 0.2 0.144 0.132 0.086 0.069 0.055 0.046 0.042 0.037 0.031 0.029 0.026 0 2000 1993 1994 1995 1996 1997 1998 1999

  9. Some of Altera’s FPGA architectures

  10. Altera FLEX 10KE Devices FLEX BREAKTHROUGH PERFORMANCE • Designed for PCI • 100-MHz System Speed • 150-MHz FIFOs Advanced Process Technology Next-Generation Packaging E • 0.25-mm CMOS SRAM • Five-Layer Metal • 2.5-V Core with MultiVolt™ I/O • 5.0-V Tolerant Inputs • 1.0-mm FineLine BGA™Packages • Requires Half the Board Area • Minimizes Cost Embedded Architecture Evolution • Dual-Port RAM • 4-Kbit EAB with x16 Width • PCI-Compliant I/O

  11. Raphael: Architectural Efficiency • MultiCore™ Architecture Integrates Three Programmable Cores • Look-up Table (LUT) Core: FLEX EPF6016 Model • Product-Term Core: MAX EPM7128 Model • RAM Core: Enhanced FLEX EAB 6016 6016 6016 6016 6016 7128 7128 7128 7128 7128 RAM RAM RAM RAM RAM 6016 6016 6016 6016 6016 7128 7128 7128 7128 7128 RAM RAM RAM RAM RAM

  12. Selected AMPP Megafunctions 8031/8051 Microcontroller Adaptive Equalizer Adaptive Filters Biorthogonal Wavelet Filter Complex Mixer/Multiplier Data Encryption Standard (DES) Digital Modulator 10/100 Ethernet MAC Discrete Cosine Transform FIR Filter Library FireWire Link Layer Controller IIR Filter Library Image Processing Library Multi-Standard ADPCM 32/64-Bit PCI Master/Target 32/64-Bit PCI Target PCI-PowerPC Bridge Reed-Solomon Decoder Reed-Solomon Encoder UARTs USB Library UTOPIA Level II for ATM Viterbi Decoder XMIDI Library

  13. APEX: Multi-Million-Gate Device • Up to 1.5-Million Usable Gates • 2.5-V and 1.8-V Families • All-Layer Copper Interconnect (APEX 20KC) • 200-MHz System Performance • Up to 442 Kb of RAM • Content Addressable Memory (CAM) APEX

  14. Selected MegaCore™ Functions Application MegaCore Function PCI DSP Error Correction Microperipherals Master/Target & Target FFT & Color Space Converters CRC Generator & Checker UARTs, Interrupt Controller, Timer

  15. ACEX: High Performance at Low Cost ACEX™ 1K ACEX 2K • 0.22-/0.18-µ Hybrid Process • 2.5-V Core and 5-V Tolerant I/Os • Up to 100K Usable Gates • 49 Kb of Dual-Port RAM • 64-Bit, 66-MHz PCI Compliant • PLL Support • 0.18-µ 6LM Process • 1.8-V Core • Up to 150K Usable Gates • Dual-Port RAM Blocks • High-Performance PLL • Advanced I/O Standard Volume Price Starting at $3.50! ACEX

  16. Development tools

  17. MegaWizard™ Plug-In • Another Industry-First Innovation from Altera • Parameterization Tool for Megafunctions • Pass Parameters to Third-Party Tools MegaWizard™ Plug-In [LPM_MULT page 3 of 6] -- Dialog TEST Number of bits of dataa input: Number of bits of datab input: 8 dataa[7..0] 13 sum[15..0] result[20..0] datab[12..0] Would you like an optional sum input? Unsigned Multiplication No Number of bits of the sum input: Yes 16 Auto size the result port width Number of bits of the sum output: 21 Cancel < Back Next > Finish

  18. Seamless Third-Party EDA Integration VHDL Verilog HDL Schematic EDIF Altera MAX+PLUS II Third-Party Design Entry Tool VHDL Output Verilog Output EDIF Output Third-Party Synthesis Tool

  19. Next-Generation Tools! METHODOLOGY DEVICES • Top-Down • Intellectual Property/Megafunctions • Workgroup Computing • Multi-Million Gates • Complex Architectural Features • Higher Performance Quartus EDA TOOL SUPPORT • Native-Live Integration • Improved Quality of Results • Robust Front-End Support NEW TECHNOLOGIES • Web/Internet • New Operating Systems

  20. Intellectual Property • 170+ Cores • Optimized for Altera Devices • Fully Tested • Easy to Customize • Development Board • Free Evaluation using OpenCoreTM Program • Communications Focus • 30 Development Partners

  21. Intellectual Property Cores Communications Bus Interface Digital Signal Processing Processor,Peripheral Ethernet MAC (10/100/Gigabit) SONET Framer T3/E3 Framer Packet Over SONET Processor Utopia Master & Slave POS-PHY Interface HDLC Protocol Core ADPCM (u-law, a-law) ATM Controller CRC IMA Controller Telephony Tone Generator PCI Target PCI Master-Target PCI-X CAN Bus IIC Master & Slave IEEE 1394 PowerPC Bus Arbiter PowerPC Bus Master PowerPC Bus Slave USB Function Controller USB Host Controller FIR Filter Compiler IIR Filter Compiler Fast Fourier Transform Reed Solomon Encoder/Decoder Viterbi Decoder Turbo Encoder/Decoder Interleaver/Deinterleaver Digital Modulator NCO Color Space Converter Discrete Cosine Transform Image Processing Library NiosTM Processor Tensilica X-tensa Processor PalmChip Bus SDRAM Controller DDR-SDRAM Controller QDR-SDRAM Controller 8237 DMA Controller 8255 Peripheral Interface 8259 Interrupt Controller 8254 Timer/Counter 8051, 6502, Z80 And More!

  22. Quartus II Development Software • Multi-Million-Gate Design • Fastest Compile Times in the Industry • Embedded Processor Support • SOPC Builder Platform • IP Encryption and Evaluation • Incremental Compilation • PowerGaugeTM Analysis Software • SignalTap® Logic Analysis • Synopsys FPGA Express Software • Mentor Graphics LeonardoSpectrum Software • Model Technology ModelSim Software

  23. System-on-a-Programmable-Chip Solution SOPC Builder Configured Silicon Features (e.g. Memory Mapping) Configured IP Cores Stripe Dual - Port DPRAM RAM Interface SRAM (Single Port) PLD SDRAM SDRAM Interface Controller Master Port Bridge Flash EBI Interface Slave Port ARM - or MIPS - PLLs Based Processor Interconnect Ports Completed SOPC Architecture

  24. Design Methodology Roadmap Hardware/SoftwareCo-Design 1M-10K Application Compilers (FIR) 100K-1M Intellectual Property (IP) Usable Gates 10-100K Behavioral VHDL/Verilog RTL 1K-5K Schematics Equations 1 1991 1993 1995 1997 1999 2001 2003 2005

  25. Complete Development Kit Offering • Altera® Nios RISC Processor • Development Tools • Quartus™ II Software • Cygnus GNUPro • Peripherals • Reference Design • Development Board & Download Cable Excalibur Development Kit,Featuring Nios $995 AvailableNow! Embedded Processor Solutions Processor Core & Compiler Licensees

  26. Future Developments

  27. Technology Impact on IC Costs Development Silicon Cost Time • ASICs Conserve Silicon Cost • PLDs Conserve Development Cost

  28. Mask & Layout Costs Over Time • Increasing Mask Layers • Finer GeometryProcesses • New Equipment Mask & Layout Costs Higher Costs RESULT

  29. Minimum Order Quantities • As Technology and Wafer Sizes Change, We Get More Net Die Per Wafer 12-inch Wafer 0.15 µ 8-inch Wafer 0.25 µ 6-inch Wafer 0.6 µ Typical Net Die Per Wafer: 30x 1x 200x This Leads to an Issue of Minimum Order Quantities...

  30. Future of System Design System on a Programmable Chip (PLD) System on a Chip (Cell-Based IC) Consumer-Oriented Products Infrastructure Products Volume Driven Lowest Unit Cost Small Form Factor Time-to-Market Driven Flexibility

  31. Souces:Altera Corporation David Greenfield,Sr. Product Marketing Manager,Development Tools

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