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FPGAs and VHDL. Lecture L12.1. FPGAs and VHDL. Field Programmable Gate Arrays (FPGAs) VHDL 2 x 1 MUX 4 x 1 MUX An Adder Binary-to-BCD Converter A Register Fibonacci Sequence Generator. Block diagram of Xilinx Spartan IIE FPGA. Each Spartan IIE CLB contains two of these CLB slices.

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Fpgas and vhdl

FPGAs and VHDL

Lecture L12.1


Fpgas and vhdl1

FPGAs and VHDL

  • Field Programmable Gate Arrays (FPGAs)

  • VHDL

    • 2 x 1 MUX

    • 4 x 1 MUX

    • An Adder

    • Binary-to-BCD Converter

    • A Register

    • Fibonacci Sequence Generator


Block diagram of xilinx spartan iie fpga

Block diagram of Xilinx Spartan IIE FPGA


Each spartan iie clb contains two of these clb slices

Each Spartan IIE CLB contains two of these CLB slices


Look up tables

A B C D Z

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 1

. . .

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

Combinatorial Logic

A

B

Z

C

D

WE

G4

G

G3

Func.

G2

Gen.

G1

Look Up Tables

Look Up Table

4-bit address

  • Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB

  • Example:

4

(2 )

2

= 64K !

  • Capacity is limited by number of inputs, not complexity

  • Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM


Introduction to vhdl

Introduction to VHDL

  • VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

  • IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide

  • VHDL enables hardware modeling from the gate level to the system level


Combinational circuit example

Combinational Circuit Example

8-line 2-to-1 Multiplexer

8-line

2 x 1 MUX

a(7:0)

y(7:0)

b(7:0)

sel y

0 a

1 b

sel


An 8 line 2 x 1 mux

a(7:0)

8-line

2 x 1

y(7:0)

MUX

b(7:0)

sel

An 8-line 2 x 1 MUX

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2 is

port (

a: in STD_LOGIC_VECTOR(7 downto 0);

b: in STD_LOGIC_VECTOR(7 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(7 downto 0)

);

end mux2;


Entity

Entity

Each entity must begin with these library and use statements

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2 is

port (

a: in STD_LOGIC_VECTOR(7 downto 0);

b: in STD_LOGIC_VECTOR(7 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(7 downto 0)

);

end mux2;

port statement defines inputs and outputs


Entity1

Entity

Mode: in or out

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2 is

port (

a: in STD_LOGIC_VECTOR(7 downto 0);

b: in STD_LOGIC_VECTOR(7 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(7 downto 0)

);

end mux2;

Data type: STD_LOGIC,

STD_LOGIC_VECTOR(7 downto 0);


Fpgas and vhdl

a(7:0)

8-line

2 x 1

y(7:0)

MUX

b(7:0)

sel

Architecture

architecture mux2_arch of mux2 is

begin

mux2_1: process(a, b, sel)

begin

if sel = '0' then

y <= a;

else

y <= b;

endif;

end process mux2_1;

end mux2_arch;

Note: <= is signal assignment


Fpgas and vhdl

Architecture

entity name

process sensitivity list

architecture mux2_arch of mux2 is

begin

mux2_1: process(a, b, sel)

begin

if sel = '0' then

y <= a;

else

y <= b;

endif;

end process mux2_1;

end mux2_arch;

Sequential statements (if…then…else) must be in a process

Note begin…end

in process

Note begin…end

in architecture


An 8 line 4 x 1 multiplexer

Sely

“00”a

“01”b

“10”c

“11”d

An 8-line 4 x 1 multiplexer

a(7:0)

8-line

b(7:0)

4 x 1

y(7:0)

c(7:0)

MUX

d(7:0)

sel(1:0)


An 8 line 4 x 1 multiplexer1

An 8-line 4 x 1 multiplexer

library IEEE;

use IEEE.std_logic_1164.all;

entity mux4 is

port (

a: in STD_LOGIC_VECTOR (7 downto 0);

b: in STD_LOGIC_VECTOR (7 downto 0);

c: in STD_LOGIC_VECTOR (7 downto 0);

d: in STD_LOGIC_VECTOR (7 downto 0);

sel: in STD_LOGIC_VECTOR (1 downto 0);

y: out STD_LOGIC_VECTOR (7 downto 0)

);

end mux4;


Example of case statement

Sely

“00”a

“01”b

“10”c

“11”d

Example of case statement

architecture mux4_arch of mux4 is

begin

process (sel, a, b, c, d)

begin

case sel is

when "00" => y <= a;

when "01" => y <= b;

when "10" => y <= c;

when others => y <= d;

end case;

end process;

end mux4_arch;

Note implies operator =>

Must include ALL posibilities

in case statement


An adder

Note: + sign synthesizes

an n-bit full adder!

An Adder

-- Title: adder

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity adder is

generic(width:positive);

port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);

b: in STD_LOGIC_VECTOR(width-1 downto 0);

y: out STD_LOGIC_VECTOR(width-1 downto 0)

);

end adder;

architecture adder_arch of adder is

begin

add1: process(a, b)

begin

y <= a + b;

endprocess add1;

end adder_arch;


Fpgas and vhdl

Binary-to-BCD Converter


Fpgas and vhdl

-- Title: Binary-to-BCD Converter

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity binbcd is

port (

B: in STD_LOGIC_VECTOR (7 downto 0);

P: out STD_LOGIC_VECTOR (9 downto 0)

);

end binbcd;


Fpgas and vhdl

architecture binbcd_arch of binbcd is

begin

bcd1: process(B)

variable z: STD_LOGIC_VECTOR (17 downto 0);

begin

for i in 0 to 17 loop

z(i) := '0';

endloop;

z(10 downto 3) := B;

for i in 0 to 4 loop

if z(11 downto 8) > 4 then

z(11 downto 8) := z(11 downto 8) + 3;

endif;

if z(15 downto 12) > 4 then

z(15 downto 12) := z(15 downto 12) + 3;

endif;

z(17 downto 1) := z(16 downto 0);

endloop;

P <= z(17 downto 8);

end process bcd1;

end binbcd_arch;


A register

A Register

-- A width-bit register

library IEEE;

use IEEE.std_logic_1164.all;

entity reg is

generic(width: positive);

port (

d: in STD_LOGIC_VECTOR (width-1 downto 0);

load: in STD_LOGIC;

clr: in STD_LOGIC;

clk: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (width-1 downto 0)

);

end reg;


Fpgas and vhdl

Register architecture

architecture reg_arch of reg is

begin

process(clk, clr)

begin

if clr = '1' then

for i in width-1 downto 0 loop

q(i) <= '0';

end loop;

elsif (clk'event and clk = '1') then

if load = '1' then

q <= d;

end if;

end if;

end process;

end reg_arch;

Infers a flip-flop for all

outputs (q)


Fpgas and vhdl

Fibonacci Sequence

-- Title: Fibonacci Sequence

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.std_logic_unsigned.all;

entity fib is

port(

clr : in std_logic;

clk : in std_logic;

P : out std_logic_vector(9 downto 0)

);

end fib;

P


Fpgas and vhdl

architecture fib_arch of fib is

component adder

generic(

width : POSITIVE);

port(

a : in std_logic_vector((width-1) downto 0);

b : in std_logic_vector((width-1) downto 0);

y : out std_logic_vector((width-1) downto 0));

endcomponent;

component reg

generic(

width : POSITIVE);

port(

d : in std_logic_vector((width-1) downto 0);

load : in std_logic;

clr : in std_logic;

set : in std_logic;

clk : in std_logic;

q : out std_logic_vector((width-1) downto 0));

end component;

Declare

components


Fpgas and vhdl

component binbcd

port(

B : in std_logic_vector(7 downto 0);

P : out std_logic_vector(9 downto 0));

end component;

signal r, s, t: std_logic_vector(7 downto 0);

signal one, zero: std_logic;

constant bus_width: positive := 8;


Fpgas and vhdl

begin

one <= '1';

zero <= '0';

U1: adder generic map(width => bus_width) port map

(a => t, b => r, y => s);

R1: reg generic map(width => bus_width) port map

(d => r, load =>one, clr => zero, set => clr,

clk =>clk, q => t);

W: reg generic map(width => bus_width) port map

(d => s, load => one, clr => clr, set => zero,

clk =>clk, q => r);

U2: binbcd port map

(B => r, P => P);

end fib_arch;

Wire up the circuit


Fibonacci sequence works

Fibonacci Sequence Works!


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