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Memory

Memory. Static RAM Dynamic RAM. Memory technology types. Read-Only Memory (ROM) Non-volatile storage ROM, PROM, EPROM, EEPROM Random Access Memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM). ROM types. OT-PROM (one time programmable) Mask ROM Fuse ROM PROM EPROM EEPROM. Word Line.

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Memory

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  1. Memory Static RAM Dynamic RAM

  2. Memory technology types • Read-Only Memory (ROM) • Non-volatile storage • ROM, PROM, EPROM, EEPROM • Random Access Memory (RAM) • Static RAM (SRAM) • Dynamic RAM (DRAM)

  3. ROM types • OT-PROM (one time programmable) • Mask ROM • Fuse ROM • PROM • EPROM • EEPROM Word Line Word Line Word Line Floating gate Bit Line Bit Line Bit Line Mask ROM Fuse ROM EPROM EEPROM Flash Memory

  4. Word Line Bit Line Bit Line Word Line Bit Line SRAM • Hold data without external refresh • Simplicity : don’t require external refresh circuitry • Speed: SRAM is faster than DRAM • Cost: several times more expensive than DRAMs • Size: take up much more space than DRAMs • Power: consume more power than DRAMs • Usage: level 1 or level 2 cache

  5. SRAM example: Samsung 1Mx4 High-speed CMOS SRAM • Fast access time: 8, 10ns (Max) • Low power dissipation • Stanby: 5mA (max) • Operating: 80 mA (8 ns), 65mA (10ns)

  6. Timing Diagram

  7. Word Line Bit Line DRAM • Refresh circuit : storage decay in ms • DRAMs take up much less space, typically ¼ the silicon area of SRAMs or less (one transistor and a capacitor)

  8. DRAM Organization Long rows to simplify refresh Two new signals: RAS, CAS Row Address Strobe Column Address Strobe replace Chip Select

  9. RAS, CAS Addressing Even to read 1 bit, an entire 64-bit row is read! Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits! Read Cycle Read Row Row Address Latched Read Bit Within Row Column Address Latched Tri-state Outputs

  10. Write cycle timing (1) Latch Row Address Read Row (2) WE low (3) CAS low: replace data bit (4) RAS high: write back the modified row (5) CAS high to complete the memory cycle

  11. RAM Refresh • Refresh Frequency:(4ms – 64ms) • 4096 word RAM -- refresh each word once every 4 ms • Assume 120ns memory access cycle • This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)! • But RAM is really organized into 64 rows • This is one refresh cycle every 62.5 ms (1 in 500 DRAM accesses) • Large capacity DRAMs have 256 rows, refresh once every 16 ms • RAS-only Refresh (RAS cycling, no CAS cycling) • External controller remembers last refreshed row • Some memory chips maintain refresh row pointer • CAS before RAS refresh: if CAS goes low before RAS, then refresh

  12. DRAM Technologies • Conventional DRAM • Fast Page Mode (FPM) DRAM • Extended Data Out (EDO) DRAM • Synchronous DRAM (SDRAM) • Double Data Rate SDRAM (DDR SDRAM) • Direct Rambus DRAM (DRDRAM) • Synchronous-Link DRAM (SLDRAM)

  13. Fast Page Mode (FPM) DRAM • Sending the row address just once for many accesses to memory in locations near each other, improving access time • Page mode • Burst mode access • Memory is not read one byte at a time (32 or 64 bits at a time) • Several consecutive chunks of memory • “x-y-y-y” for four consecutive accesses

  14. Example: Samsung 1Mx16 FPM DRAM • Power : 5V or 3.3 V, 450-500 mW • Access time : 50ns, 60ns

  15. EDO DRAM: Samsung 1Mx16bit

  16. Synchronous DRAM • Tied to the system clock • Burst mode • System timing : 5-1-1-1 • Internal interleaving • New memory standard for modern PCs • Speed • Access time: 10ns, 12ns,… • MHz rating: 100 MHz, 133MHz

  17. Synchronous DRAM, cont’d • Latency • SDRAMs are still DRAMs • 5-1-1-1 (10ns means the second, third and fourth access times) • 2-clock and 4-clock Circuitry • 2-clock: 2 different DRAM chips on the module • 4-clock: 4 different DRAM chips • Packaging • Usually comes in DIMM packaging • Buffered and unbuffered, 3.3 V and 5.0V

  18. Samsung 8Mx8bitx4 banks synchronous DRAM

  19. SDRAM DIMM • 64Mx64 SDRAM DIMM based on 32Mx8, 4 banks 3.3v SDRAMs with SPD • SPD: serial presence detect chip: speed and design information about the module

  20. Direct Rambus DRAM (DRDRAM) • Direct Rambus channel • High speed 16-bit bus, 400MHz • Transfers at rising and falling edges, 1.6Gbytes/second • Rambus Inline Memory module (RIMM)

  21. Samsung 256/288Mbit RDRAM • 512K x 16/18 x 32s banks • Mobile, graphics, and large memory systems • Low latency • Advanced power management

  22. Synchronous-Link DRAM (SLDRAM) • SLDRAM Consortium • Evolutionary design • 64bit bus running at a 200 MHz clock speed (effective speed of 400 MHz) • 3.2 Gbytes/second • Open standard

  23. Comparison of semiconductor memories * 0.4 mm design rule

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