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FPGA 138.24MSPS DATA

1.1 Customer Concept. sampling frequency : 138.24MHz / Interpolation : 4x Enable Digital Mixer fs /2 Disable NCO. FPGA 138.24MSPS DATA. ADC. DAC3484. 241.92MHz. 241.92MHz. Testing for TSW1400 + DAC3484 EVM. 1. Test Configuration. Signal Generator. Spectrum. TSW1400. DAC34H84EVM.

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FPGA 138.24MSPS DATA

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  1. 1.1 Customer Concept • sampling frequency : 138.24MHz / Interpolation : 4x • EnableDigital Mixer fs/2 • Disable NCO FPGA 138.24MSPS DATA ADC DAC3484 241.92MHz 241.92MHz

  2. Testing for TSW1400 + DAC3484 EVM

  3. 1. Test Configuration Signal Generator Spectrum TSW1400 DAC34H84EVM PC

  4. 3. Test Result - Signal source file: single tone - F sampling frequency : 307.2MHz / Interpolation : 4x [TSW1400] [DAC3484] [DAC34H84 Register] [Spectrum] Test Result : Normal

  5. 3. Test Result - Signal source file: WCDMA_TM1_complexIF30MHz_Fdata307.2MHz_1000 - F sampling frequency : 307.2MHz / Interpolation : 4x If see below spectrum capture, Sidelobe graph don’t clean. This condition is a problem in system properties. Please check register setting [TSW1400] [DAC3484] [DAC34H84 Register] [Spectrum] Test Result : PLL LOCK Normal

  6. 3. Test Result - Signal source file: WCDMA_TM1_complexIF30MHz_Fdata307.2MHz_1000 - F sampling frequency : 307.2MHz / Interpolation : 2x [TSW1400] [DAC3484] [DAC34H84 Register] [Spectrum] Test Result : Normal

  7. 3. Test Result - Signal source file: single tone - F sampling frequency : 138.24MHz / Interpolation : 2x PLL lock does not. Please check register setting. [TSW1400] [DAC3484] PLL unlock [DAC34H84 Register] [Spectrum] Test Result : Abnormal Signal unstable Center Freq mismatch

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