SysPy: Using Python for processor-centric SoC design

1. SysPy: Using Python for processor-centric SoC design Evangelos Logaras Elias S. Manolakos {evlog, eliasm@di.uoa.gr} Department of Informatics and Telecommunications University of Athens, Greece IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2010, Athens, Greece IEEE ICECS 2010

2. Processor – centric design • SoCs are largely structured with a microprocessor-centric view. • Software plays a key role in modern SoC systems  hardware/software co-design. • Processors are available as Intellectual Property (IP) cores in netlist or HDL formats. IEEE ICECS 2010

3. Processor – centric design Processor as an IP core Single chip processor IEEE ICECS 2010

4. Why Python for SoC design? • Python is a high level programming language which supports structured and object-oriented programming. • Python combines remarkable power with very clean and simple syntax. • The language adopts dynamic typing and has a large variety of supported data types. • C/C++ functions can be imported and used. IEEE ICECS 2010

5. High – level abstraction • Our objective is to create a tool which can handle both the hardware and the software aspects of a SoCs design flow. • SysPy can be used to describe hardware components (IP cores) as well as the software assigned to run in a soft processor of the SoC. • Innovation: Python is used to describe SoC elements and glue them in a system. IEEE ICECS 2010

6. State of the art – Python based CAD System Python IEEE ICECS 2010

7. State of the art • PyCells are parameterized cells for ASIC design (analog design) described in Python. • PyHDL uses Python just for structural descriptions, using predefined blocks. • MyHDL can be used instead of a classical HDL to describe a hardware module.  SysPy covers the features of MyHDL, and in addition supports a complete MPSoC design flow by incorporating also the use of programmable processor soft-cores. IEEE ICECS 2010

8. SysPy features Python – to – VHDL conversion (Python as an HDL) - completed Integration into a design of different components, expressed in Python, VHDL, netlists - completed Hw/Sw co-design of SoCs using Python - progress System-level simulation – in planning phase IEEE ICECS 2010

9. SysPy Design flow (EDIF) Fig. Design flow with SysPy. IEEE ICECS 2010

10. Python – to – VHDL conversion Baseline: convert Python component descriptions to equivalent synthesizable VHDL descriptions. Guarantee that VHDL code is correct (syntax, signal assignment and declaration-wise etc.). The conversion is optimized for the Xilinx XST synthesizer. IEEE ICECS 2010

11. Modular design with different components • Components that SysPy can integrate into a SoC: • Python-described components (SysPy translates them to VHDL components). • Already existing VHDL components supplied by the designer. • Components from 3rd party VHDL libraries (e.g. Xilinx Unisim). • Pre-synthesized netlist components (e.g. Xilinx CoreLib). IEEE ICECS 2010

12. Hw/Sw co-design of SoCs Embedded softcore processor modules can be connected to custom IP components at the top level Python description of the SoC. The softcore processor’s code should be expressed in C. SysPy automatically calls gcc, compiles the C code and creates a VHDL component, that corresponds to a Block RAM – based memory structure, initialized with the executable code. SysPy currently supports an AVR microcontroller open IP core. Plans to target OpenRisc and LEON 32-bit processor IP cores are under the way. IEEE ICECS 2010

13. SoC design example • We have used SysPy todesign a processor-centric SoC systemthat applies Sobel edge detectionto grayscale images. • Sobel’s algorithm functions have been partitioned to: • an AVR core, which handles all memorymanagement and data manipulation and, • to an application application specific accelerator described as a Finite State Machine (FSM). • A Virtex-5 FPGA device has been used for the implementation. IEEE ICECS 2010

14. SoC design example Fig. Implementation of Sobel edge detection using SysPy. IEEE ICECS 2010

15. SoC design example • Device utilization for the Xilinx Virtex-5 LX110T FPGA device: • The design can be clocked as high as > 300MHz. IEEE ICECS 2010

16. Future work Support for 32-bit softcore processors (LEON, OpenRisc). Processors supported by the gcc tools will be preferred. Performing system-level design exploration in Python by expressing also the processors code in Python syntax (popular with the Bioinformatics community). Tools for Python – to – C conversion will be investigated. Mapping complex arithmetic functions to special structural blocks (DSP algorithmic descriptions). IEEE ICECS 2010

17. Future work • A simulation mechanism will be developed for co-simulation of the Python descriptions. • Simulated code will be synthesizable without any modifications. • Test the design with more elaborate applications, e.g. image/video processing applications, bioinformatics applications etc. • Supporting ASIC design and producing VHDL code compatible with Synopsys standard-cell design tools. IEEE ICECS 2010

18. Thank you! IEEE ICECS 2010

19. Backup slides IEEE ICECS 2010

20. Why Python for system-level design? • At least three projects have already used Python for hardware design. • Most of them (PyHDL based on PAM-Blox) use Python just for structural descriptions, using component libraries. • MyHDL supports the three basic hardware description methods, e.g. behavioral, dataflow and structural. It can perform a behavioral simulation of a module. • However, MyHDL lacks the ability to embed ready-to-use components from commercial or user-defined component libraries. IEEE ICECS 2010

21. Why Python for system-level design? • Furthermore, MyHDL does not take into account the software aspects of a SoC since it does not have any provision for handling processor IP cores. • SysPy supports all three basic HDL description styles, and in addition supports predefined blocks and programmable processor softcores. • SysPy not only support incremental module-level design for synthesis but goes all the way to support hw/sw co-design and simulation of modular embedded MPSoCs. IEEE ICECS 2010

22. SysPy coding example (bridge component) IEEE ICECS 2010

23. SysPy coding example (cont.) IEEE ICECS 2010