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GA-M59SLI-S5 introduction

GA-M59SLI-S5 introduction. nForce 500 Series Chipset. nForce 550 Block Diagram. nForce 570 Ultra Block Diagram. nForce 570 SLI Block Diagram. nForce 590 Block Diagram. Legacy. Management Processor. MCP55PXE Diagram. SATA 3 Gb/s. Serial ATA 3 Gb/ s. PCI Express. Serial ATA 3 Gb/ s.

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GA-M59SLI-S5 introduction

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  1. GA-M59SLI-S5 introduction

  2. nForce 500 Series Chipset

  3. nForce 550 Block Diagram

  4. nForce 570 Ultra Block Diagram

  5. nForce 570 SLI Block Diagram

  6. nForce 590 Block Diagram

  7. Legacy Management Processor MCP55PXE Diagram SATA 3 Gb/s Serial ATA 3 Gb/ s PCI Express Serial ATA 3 Gb/ s Serial ATA 3 Gb/ s 2 Drives PCI-33 10 Ports Internal Bus LPC BUS RGMII/MII RGMII SMBus HDA RS232 Hyper Transport Interface Hyper Transport Link NVIDIA SPP

  8. External PCI Express Device External PCI Express Device External PCI Express Device C51XE Diagram MCP51XE Hyper Transport Link @ 1 GHz Hyper Transport Interface x1 PCI Express x1 Root Port Internal Bus x1 PCI Express x1 Root Port x16 PCI Express x16 Root Port Active Power Management Integrated Clock Synthesizer Hyper Transport Interface Hyper Transport Link @ 1 GHz AMD Athlon 64/Athlon 64 FX Processors

  9. GA-M59SLI-S5 BLOCK DIAGRAM

  10. Power On Off Circuitry 5VSB→5VDUAL 25.00MHZ 32.768KHZ 3VDUAL 3VDUAL RTCVDD -RTCRST BATTERY nVIDIA MCP55P VBAT VCC12DUAL PWRBTSW SLP_S3 5VSB System On-Off Button PSIN SB_PWOK -PWRBTSW ATX Power Supply -IO_PSON PS ON# IT8716

  11. System Reset Map PCIE_RST# HT_CPU_PWRGD PCIE_1 AMD K8 AM2 C51XE PCIE_16_1 HT_CPU_RST# PCIE_2 HTMCP_PWRGD PCIE_8 HTMCP_RST# PCIE_16_2 ATX SLP_S3# PS ON PWRGD PCI SLOT PWOK PPCIRST#_SLOT1 PPCIRST#_SLOT2 MCP55P ALC888 ACZ_RST# IDERST# 1394RST# LPCRST_SIO# LPCRST_FLASH# MII_RST# IDE SB_PWOK DUAL BIOS IEEE 1394 TSB43AB23 MARVELL 88E1116 MARVELL 88E1116 ITE 8716GB/CX

  12. C51XE/MCP55PXE Power Sequencing Block Diagram AMD K8 AM2 HT_CPU_PWRGD HT_CPU_RST# HT_CPU_UP HT_CPU_DN CPU_CLK PRSNT# PERST# C51XE PE_REFCLK# HT_MCP_PWRGD HT_STOP# HT_MCP_RST# HT_MCP_UP HT_MCP_DN CR_REF_CLK HT_REQ# PCIRST# HT_VLD HT_VDD_EN CPU_VLD MCP55P CPU_VDD_EN MEM_VLD SLP_S3# CK8_PWOK SLP_S5# SB_PWOK LPC_PD# ROM

  13. Super I/O LPC_CLK0 BUF_SIO_CLK LPC_CLK1 BIOS HDA CODEC HDA_BCLK XTALIN PE0_REFCLK_N PEX X 16 XTALOUT PE0_REFCLK_P PE5_REFCLK_N PE3_REFCLK_N PEX X 8 PEX X 1 PE5_REFCLK_P PE3_REFCLK_P XTALIN_RTC XTALOUT_RTC PE1_REFCLK_N PEX X 1 HT_MCP_RX_CLK[0:1]_N PE1_REFCLK_P PCICLK1 PCI_CLK0 HT_MCP_RX_CLK[0:1]_P PCI_CLK1 HT_MCP_TX_CLK[0:1]_N PCICLK2 PCI_CLK2 TPM HT_MCP_TX_CLK[0:1]_P PCI_CLK3 1394CLK CLKOUT 200MHZ_N PCI_CLK4 PE2_REFCLK_N GIGABYTE SATA 2 CLKOUT 200MHZ_P PCI_CLK5 PE2_REFCLK_P CLKOUT_25MHZ PCI_CLKIN CLKIN_25MHZ CLKIN 200MHZ_N CLKIN 200MHZ_P PE0_REFCLK_N PEX X 16 HT_MCP_RX_CLK[0:1]_N PE0_REFCLK_P HT_MCP_RX_CLK[0:1]_P PE1_REFCLK_N HT_MCP_TX_CLK[0:1]_N PE1_REFCLK_P HT_MCP_TX_CLK[0:1]_P HT_CPU_RX_CLK[0:1]_N PE2_REFCLK_N HT_CPU_RX_CLK[0:1]_P PE2_REFCLK_P HT_CPU_TX_CLK[0:1]_N HT_CPU_TX_CLK[0:1]_P CLKOUT 200MHZ_N CLKOUT 200MHZ_P MA0_CLK[2:0]_N CLKIN 200MHZ_N DIMM 0 MEM_A0 MA0_CLK[2:0]_P CLKIN 200MHZ_P MB0_CLK[2:0]_N DIMM 0 MEM_B0 HT_CPU_RX_CLK[0:1]_N MB0_CLK[2:0]_P HT_CPU_RX_CLK[0:1]_P MA1_CLK[2:0]_N DIMM 0 MEM_A1 MA1_CLK[2:0]_P HT_CPU_TX_CLK[0:1]_N MB1_CLK[2:0]_N DIMM 0 MEM_B1 HT_CPU_TX_CLK[0:1]_P MB1_CLK[2:0]_P GA-M59SLI-S5 System Clock

  14. Power-Up Sequence *Core Planes include: +1.2V Core, +1.5V_PLL_HT, +3.3V_PLL_HT, +1.5V_PE_PLL_AVDD, +1.5V_PE_PLL_DVDD, +1.5V_PE_PLL_CORE +1.5V_PE_D, +1.5V_PE_A, +3.3V_PE_PLL_CORE, +1.5V_SP_PLL_AVDD, +1.5V_SP_PLL_DVDD, +1.5V_SP_PLL_CORE +1.5V_SP_D, +1.5V_SP_A, +3.3V_SP_PLL_CORE, +3.3V_PLL_CPU, +3.3V_PLL_USB +3.3V, +5.0V_CLAMP

  15. AMD Socket 939 Architecture

  16. AMD Socket 940 Architecture

  17. CPU HYPER TRANSPORT INTERFACE

  18. AMD CPU CTLOUT0_H HT_RXCTL_P CTLOUT0_L HT_RXCTL_N CADOUT(7:0)_H HT_RXCAD[7:0]_P CADOUT(7:0)_L HT_RXCAD[7:0]_L HT_RXCLK0_P CLKOUT0_H CTLOUT1_H VCC12_HT CLKOUT0_L HT_RXCLK0_L CTLOUT1_L GND CADOUT(15:8)_H HT_RXCAD[15:8]_P HT_RXCAD[15:8]_L CADOUT(15:8)_L HT_RXCLK1_P CLKOUT1_H CLKOUT1_L HT_RXCLK1_N CTLIN0_H HT_TXCTL_P HT_TXCTL_N CTLIN0_L HT_TXCAD[7:0]_P CADIN(7:0)_H HT_TXCAD[7:0]_L CADIN(7:0)_L HT_TXCLK0_P CLKIN0_H CLKIN0_L HT_TXCLK0_L HT_TXCAD[15:8]_P CADIN(15:8)_H HT_TXCAD[15:8]_L CADIN(15:8)_L HT_TXCLK1_P CLKIN1_H CLKIN1_L HT_TXCLK1_L PWROK (CPU_PWRGD) LDTRST_L (-CPURST) LDTSTOP_L (HTSTOP_L) Hyper Transport Link Interconnect

  19. Memory Interface Channel A

  20. Memory Interface Channel B

  21. DDR2 SDRAM Memory Interface Pin Descriptions

  22. MB1_CLK_H[2:0], MB1_CLK_L[2:0] MA1_CLK_H[2:0], MA1_CLK_L[2:0] MB0_CLK_H[2:0], MB0_CLK_L[2:0] MA0_CLK_H[2:0], MA0_CLK_L[2:0] MA_ADD[15:0], MA_BANK[2:0] MA_RAS_L,MA_CAS_L,MA_WE_L MB_ADD[15:0], MB_BANK[2:0] MB_RAS_L,MB_CAS_L,MB_WE_L AM2 Socket Processor MA0_CS_L[1:0],MA_CKE[0],MA0_ODT[0] MA1_CS_L[1:0],MA_CKE[1],MA1_ODT[0] MB0_CS_L[1:0],MB_CKE[0],MB0_ODT[0] MB1_CS_L[1:0],MB_CKE[1],MB1_ODT[0] Unbuffered DDR2 SDRAM 240 DIMM Unbuffered DDR2 SDRAM 240 DIMM MA_DATA[63:0],MA_CHECK[7:0] Unbuffered DDR2 SDRAM 240 DIMM Unbuffered DDR2 SDRAM 240 DIMM MA_DQS_H[8:0],MA_DQS_L[8:0] MA_DM[8:0] MB_DATA[63:0],MB_CHECK[7:0] MB_DQS_H[8:0],MB_DQS_L[8:0] MB_DM[8:0] DIMM A0 DIMM B0 DIMM A1 DIMM B1 Unbuffered 4-DIMM Block Diagram

  23. Power-Up Signal Sequencing

  24. CPU VCORE

  25. MCP55XE Power

  26. MCP55XE Power (Cont)

  27. +5V RTCVDD +3.3V_VBAT +5V VCC12_HTMCP +1.2V_DUAL +1.2V_HT +1.5V +1.5V_PEA +1.5V_PLL_CPU_HT +1.5V_PLL_PE_SS +1.5V_PLL_PE +1.5V_PLL_SP_SS +1.5V_PLL_SP_VDD +1.5V_PLL_USB +1.5V_SP_A +1.5V_SP_D +1.2V VCC15V +3.3V_DUAL +3.3V_USB_DUAL +3.3V_PLL_MAC_DUAL 3VDUAL VCC3 +3.3V +3.3V_HT +3.3V_PLL_CPU +3.3V_PLL_HT +3.3V_PLL_USB +3.3V_PLL_PE_SS +3.3V_PLL_SP_SS VCC12DUAL

  28. C51XE Power Description

  29. C51XE Power Description (cont)

  30. C51XE POWER

  31. 5VSB 5VDUAL

  32. 5VDUAL3VDUAL

  33. 3VDUALVCC12DUAL

  34. DDRV18V

  35. S5_EN

  36. DDRVTT

  37. VCC15

  38. VCC12

  39. VCC12_HT

  40. VCC12_HTMCP

  41. VDDA25

  42. VCC2P5V_PWR

  43. CK8_ PWOK

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