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Reducing memory penalty by a programmable prefetch engine for on-chip caches. Presentatie voor het vak computerarchitectuur door Armin van der Togt. Indeling:. Probleemstelling De prefetch architectuur Resultaten Conclusies Gerelateerd werk. Probleemstelling.

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reducing memory penalty by a programmable prefetch engine for on chip caches

Reducing memory penalty by a programmable prefetch engine for on-chip caches

Presentatie voor het vak computerarchitectuur door

Armin van der Togt

indeling
Indeling:
  • Probleemstelling
  • De prefetch architectuur
  • Resultaten
  • Conclusies
  • Gerelateerd werk
probleemstelling
Probleemstelling
  • Verschil tussen snelheid van geheugen en CPU wordt steeds groter dus: cache en prefetching
  • Hardware prefetching duur en complexe geheugen structuren moeilijk
  • Software prefetching veel executie overhead
software prefetching
Original code

Generated code

(inner loop only)

Software prefetching
de prefetch architectuur
Hare

Prefetch

Engine

Firing

ALU

on-chip

cache

De prefetch architectuur

Run-Ahead Table

PC

ORQ

Memory

system

Processor chip

slide6
iaddr: PC om prefetch te starten

: prefetch adres en stapgrootte

: prefetch condities

count: eens in de count keer dat PC=iaddr wordt een prefetch gestart

start: pas na start keer dat aan de bovenstaande conditie is voldaan mag begonnen worden met prefetchen

Nieuwe instructie voor de prefetch engine:

fill_run_ahead iaddr, ,

slide8
Code met prefetch instructies

memory latency

=

5 cycles

conclusies
Conclusies
  • Prefetching kan geheugen penalty tot 80% verlagen
  • Een programeerbare prefetch engine verlaagt de penalty ten opzichte van software prefetching
  • Bij kleine caches (1-2k) is de programmerbare prefetch engine relatief duur
  • de compiler moet prefetching ondersteunen
gerelateerd werk
Gerelateerd werk
  • Fu and Patel: stride directed prefetching in scalar processors (hardware)
  • Mowry and Gupta: software controlled prefetching
  • Chiueh: A programmable hardware prefetch architecture for numerical loops (lijkt hier op)
literatuur
Literatuur
  • Tien-Fu Chen, Reducing memory penalty by a programmable prefetch engine for on-chip caches, Microprocessors and Microsystems, 21 (1997) 121-130
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