Introduction to VHDL (part 2)

1. Introduction to VHDL (part 2) EE 162 Digital Circuit Design Vojin Oklobdzija by Vishal Nawathe

2. Quick Review of last lecture… • What is VHDL? • Why VHDL? • Essential components for VHDL • Types of circuit descriptions in VHDL • All statements in VHDL are _________ • Concept of ∆ delay • Usage of ‘after’ keyword • Signal types discussed earlier • Questions till now???

3. VHDL Code for V.1 library ieee; use ieee.std_logic_1164.all; entity latch is port (A,B,C: in bit; J: out bit); end latch; architecture dataflow of latch is signal D, E, G : bit; begin G <= not A and not B and C; E <= B and D; D <= A and not C; J <= G and E; end dataflow;

4. Behavioral Description • Unlike the other two methods for describing the architecture, behavioral description is like a black box approach to modeling a circuit • It is designed to do a specific task, how it does it - is irrelevant • It is used to model complex components which are hard to model using basic design elements • Behavioral descriptions are often more powerful and allow for easy implementation of the design

5. Behavioral Description (contd.) • They are supported inside a ‘process’ statement • A ‘process’ is used to describe complex behaviors of the circuit • The contents of a process can include sequential statements • These sequential statements are similar to commands in conventional programming languages (it, for, etc) which can only be used in the body of a process statement • Although, inside a process is sequential, the process itself is concurrent, all processes in an architecture begin execution at the same time • The process statement is declared in the body of the architecture similar to signal assignments in data flow

6. Elements of a Process • Processes can have a list of signals that they depend on, a sensitivity list, or they can use wait signals to make the process wait for a event to occur (not both) • They are only to execute if the signals in the sensitivity list change • This makes it critical to ensure that the signals on which a process depends-on are in the sensitivity list • Can we generate a clock signal with this knowledge??? Process label (optional) Process is dependent only on variable “x” count: process (x) variable count : integer := -1; begin count:=count + 1; end process Similar to equals ‘=‘ Increments the variable “cnt” every time the signal of “x” changes

7. Variables • Variables in VHDL behave similar to those in conventional programming languages • For e.g. in C, we define integer variable as: • int x = -1; • They are used to represent the state of a process and are local to that process • As in C, variables are local to the function they are declared in • They are declared in a similar way to that of a signal in data flow or structural descriptions variable count : integer := -1; • As shown in the example in previous slide, variables are declared before the begin keyword of a process

8. Variables and signals signal x, y, z : bit; process (y) begin x<=y; z<=not x; end process process (y) variable x,z : bit; begin x:= y; z:= not x; end process; • It should be realized that signals and variables are different. On the left both commands in the process are concurrent, they occur at the same time. This results in ‘z’ not being inverse of ‘y’ but the inverse value of ‘x’ when the process begins • For the example to the right, variables are used, which are sequential, hence the value of ‘z’ is the complement of ‘y’. • Signal assignment statements do not take effect immediately • Variable assignments take effect immediately

9. r q nq s Behavioral vs. Structural vs. Data flow Structural How components are put together Data Flow Describes how data flows from input to output process (r,s) begin if (r nor nq) then q <= ‘1’; else q <= ‘0’; endif . . . end process Behavioral Describes the behavior of the circuit within a process

10. ‘Wait’ statement • Causes execution of sequential statements to wait • Should be ‘inside’ a process statement • [ label: ] wait [ sensitivity clause ] [ condition clause ] ; • waitfor 10 ns; -- timeout clause, specific time delay. • waituntilclk='1'; -- condition clause, Boolean condition • waituntil A>B and S1 or S2; -- condition clause, Boolean condition • waiton sig1, sig2; -- sensitivity clause, any event on any signal terminates wait

11. Conditional statements : ‘if’ • Syntax : • [ label: ] if condition1 then • sequence-of-statements • elsifcondition2 then • optional sequence-of-statements • elsifcondition3 then • optional sequence-of-statements • else • optional sequence-of-statements • end if [ label ] ; • Example : • if a=b then • c:=a; • elsifb<c then • d:=b; b:=c; • else c:=a; • endif;

12. Conditional statements : ‘switch - case’ • Execute one specific case of an expression equal to a choice • The choices must be constants and of the same data type as the expression • Syntax : • [ label: ] case expression is • when choice1 => sequence-of-statements • when choice2 => optional sequence-of-statements • when others => optional if all choices covered sequence-of-statements • end case [ label ] ; • Example : • casemy_valis • when1 => a:=b; • when3 => c:=d; do_it; • whenothers => null; • endcase;

13. Loops : ‘for’ • Syntax : • Optional_label : for parameter in range loop • sequential statements • end loop Optional_label; • Example : • begin • forI in 1 to 10 loop • if (REPEAT = '1') then • I := I-1; -- Incorrect logic • end if; • end loop;

14. Loops : ‘while’ • Syntax : • Optional_label : whilecondition loop • sequential statements • end loop Optional_label; • Example : • begin • whileNOW < MAX_SIM_TIME loop • CLK <= not CLK ; • wait for PERIOD/2; • end loop; • wait; • end process;

15. Example : V.2 • Generate a 4-bit right shift register with synchronous reset. The bits shift to the right – one at a time at rising edge of the ‘clk’ signal. • What will be the change if the reset is made ‘asynchronous’?

16. VHDL code for V.2 • entity rsris • Port (clk, clr, ld, rs, lin: in bit; • d: in bit_vector(3 downto0); • q: out bit_vector(3 downto0)); • end rsr; • architecture behavioral of rsris • signal qint: bit_vector(3 downto0); • begin • q <= qint; • process (clk) • begin • if clk’eventand clk ’1’ then • if clr= ’1’ then qint<= “0000”; • elsifld= ’1’ then qint<= d; • elsifrs= ’1’ then qint<= lin & qint(3 downto1); • end if; • end if; • end process; • end behavioral;

17. Thank You