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FT-UNSHADES2.

FT-UNSHADES2. . H.G . Miranda, M.A. Aguirre , J. Barrientos , L. Sanz Electronic Engineering Dpt. School of Engineering. University of Sevilla (SPAIN). Sevilla , March 2014. FT-UNSHADES goals. FT-UNSHADES is a tool for SEE EMULATION, at netlist level.

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FT-UNSHADES2.

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  1. FT-UNSHADES2. H.G. Miranda, M.A. Aguirre, J. Barrientos, L. Sanz Electronic Engineering Dpt. School of Engineering. University of Sevilla (SPAIN) Sevilla, March 2014

  2. FT-UNSHADES goals • FT-UNSHADES is a tool for SEE EMULATION, at netlist level. • Emulation is the use of programmable hardware structures to perturb the design under test. • It is a highly flexible and simple solution from the designer point of view. • The goal is to perform the injections in a deterministic manner. • Combines Massive Injections with cycle accurate analysis, in the same tool • Exploits the mechanisms of Xilinx FPGA, named Partial Reconfiguration, Snapshot and Readback Other features: • Remote access • Internal analysis • Test in the beam • Targeting FPGAs for analysis

  3. What for, FTU2? Check the protection level Hierarchical assessment of the submodules Check protections Selective redundancies Reset and initialization policy Digital SETs MBU studies SEE detailed analysis

  4. FT-UNSHADES2 in a ASIC mode • FTU2 is a contract with ESA: “High Capacity, High Speed IC Test SystemforAutomaticFaultInjection and Analysis (FT-UNSHADES 2)” • FTU2 is a platform designed to assess the reliability of a netlist at design level. • The processing is determined knowing a priori where, when and how to inject the faults over USER REGISTERS. • In FTU2 both sights are implemented: fault campaigns and single fault detailed analysis • Several SEEs models are implemented: SEU and MBU, and under certain conditions, SETs. • The design flow has been is reduced to a FPGA standard implementation and a simulation. • The PARTIAL RECONFIGURATION feature of Xilinx FPGAs is exploited to generate bit-flips into the USER REGISTERS, LUTs, BRAMs…

  5. FTU2 in FPGA mode Originally FTU was thought trough the assessment of ASIC netlist. FTU2 has been extended to inject on SRAM-FPGAs configuration. • The basic mechanism to inject over the FPGA CONFIGURATION is the same than USER REGISTERS. • It is not constrained to a specific FPGA • Analyzes in detail the propagation of a fault in the configuration, and the possible corruption of the user logic. • The study of techniques for scrubbing policy

  6. FT-UNSHADES2 in a nutshell: the structure of the hardware Target FPGA I / Os Two twin FPGAs hosts two copies of the netlist. The design runs along in parallel • Bitstream • Injection Batch • Workload Control FPGA M A SELECTMAP R D Target FPGA I / Os

  7. FT-UNSHADES2 in a nutshell: the structure of the hardware Target FPGA DRAM Memory Service FPGA Control FPGA

  8. FT-UNSHADES2 in a nutshell: the design preparation flow • Bitstream (.bit) • Bit allocation file (.ll) • Port location (.pin) • VCD stimuli (*.vcd) • For FPGA flow • Configuration allocation (*.cl) • Fit your design in the target FPGA • Allocate I/Os • Simulate and extract inputs • Finish the standard flow

  9. LOCAL COMPUTER FTUNSHADES SERVER Design.pin MakeUser ConstraintsFile Design.pin Design.ucf Design (HDL) Simulation ISE Makestimuli file Design.dat Design.vcd Xilinx Synthesis & PAR Design.bit Design.bit Design.ll Design.ll FTU2 files

  10. THE HARDWARE….

  11. FTU2: Physical Layer • FTU2 isbuiltfrom a MB and 2 DBs: • The MB is a Xilinx ML510 PCI socket for USB interface withthe server PCIE sockets fortheDBs Control FPGA (XC5VFX130T) DDR2 sockets for DIMM modules (512MB)

  12. FTU2: Physical Layer • FTU2 isbuiltfrom a MB and 2 DBs: • Thedesign of the DB isoriginal ATXpowerconnector PCIE x16 cardedge Target FPGA V5 FF1136 Package Service FPGA (XC5VFX70T)

  13. FTU2: Physical Layer • FTU2 isbuiltfrom a MB and 2 DBs: • Thedesign of the DB isoriginal • Virtex5 FF1136 package: • XC5VLX50T • XC5VLX85T • XC5VLX110T • XC5VLX155T • XC5VSX50T • XC5VSX95T • XC5VFX70T • XC5VFX100T

  14. FTU2: Physical Layer • FTU2 islinkedtotheuff-tnt server via USB: • FTDI FT2232HQ minimodule: • Configured as USB to FIFO • Two interfaces available • USB2.0

  15. FTU2: Physical Layer • Thesystemisassembledintoan ATX tower Motherboard GOLDDaughterboard SEU Daughterboard USB-PCI board holding the 2232H minimodule

  16. THE FIMWARE AND THE SOFTWARE…

  17. FT-Unshades2 Firmware • Functionality has beendividedbetweenallfiveFPGAs: • Control FPGA: Experiment control, communicationswith PC • “Gold” Service-FPGA: Feedstimuli, sample responses • “Seu” Service-FPGA: Feedstimuli, sample responses, InjectFaults • “Gold” Target-FPGA: 100% User design! • “Seu” Target-FPGA: 100% User design!

  18. FT-Unshades2 Firmware

  19. FT-Unshades2 Firmware • Interestingfeatures: • PCIexpressphysicallayer • Serializestimuli and responses. Allowup to 512 I/Os forthe Target FPGA. • EachPCIeendpointallows up to 2 Gbps of user data (full duplex) • Embedded bit-flipinjector • Mainbottleneck in FTU1 was in thepartialreconfigurationprocedureusedtoinjectthefaults: frameshadtotraveltothe PC to be modified and back againtotheboard • DDR2 Memorycontroller: • Up to 512 MB forbitstream + stimuli + batchcommands

  20. FT-Unshades2 FW: Lessons Learned • Embeddedbitstreammanipulation module solvesbottleneckdetected in previousversion (FTU1) • Manipulatingstimuli and responses withthe PPC creates a new bottleneck • PPC isgreatforprototyping, but sub-optimalforspeed • Bottleneck emerges withlargenumber of test vectors • Good news: This can be solvedwithoutmodifyingthe hardware, onlywithfirmware updates • 1st step: Comparison module: increasespeedifusingcompressedstimuli • 2nd step: Vector feeder: increasespeedbyskipping PPC whenreadingfrom DDR2

  21. FT-Unshades2 Software • Solvescomplexity and presentsanUserFriendly Framework

  22. FTU2 in numbers • Fault rate achieved: 10.000 faults/sec (this figure will be improved in new versions) • 512 I/Os, the capacity depends on the model of the target device. • Current configurations Virtex 5, LX50T and FX70T (FF1136 package)

  23. FTU2 future actions • Improve the fault rate • Continue the development of FTU2-UFF • Construct a “farm” of devices, support the system • Work with the “microprocessor mode” • Extend the system to a test fixture for beam testing and diagnose • Go ahead with the FPGA mode

  24. Access to FTU2 For Academia: • Access is available to public academia for research purposes via internet. • An agreement between the third institution and the USE • User/Password is given • Also support beta users coordinated by ESA For industrial customers: • An agreement with UoS • Training and support • Install the FTU2 in their headquarter intranet • Sell the system and support

  25. Thank you for your attention Q &A Contacts: aguirre@gie.esi.us.es hipolito@gie.esi.us.es david.merodio.codinachs@esa.int

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