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Baseline Board B. Carlson

This document provides an overview of the EVLA Correlator CDR Baseline Board, including its components, power distribution, and test results.

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Baseline Board B. Carlson

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  1. Baseline BoardB. Carlson EVLA Correlator CDR Dec. 2-3, 2008

  2. Outline • Board overview • RXP FPGA • Recirculation FPGA • Correlator Chip • LTA • GigE FPGA • Power distribution. • Overall board test status and test results EVLA Correlator CDR - Baseline Board

  3. Overview • Multiple 1.024 Gbps receivers and 8 x 8 systolic array of lag correlator chips. • 12 U x 400 mm form factor. • 28 layers, ~100,000 solder points. • 64xF672 ASICS, 19xF672 FPGAs, 68xF256 FPGAs, 64xTSSOP64 DDR SDRAMs, 32xF256 DPSRAMs, 64x5 mm QFNs, 96x3 mm QFNs, PC/104+ mezzanine card, etc. • 500 W power dissipation at full power. 120 W quiescent power (no FPGAs programmed). EVLA Correlator CDR - Baseline Board

  4. EVLA Correlator CDR - Baseline Board

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  7. EVLA Correlator CDR - Baseline Board

  8. RXP FPGA • RXP – “Re-timing, X-bar, and Phasing” FPGA. • Receives and re-times 64 Gbps of DATA, and 32 Gbps of CNTRL from Station Boards. • 1 sub-band pair from all 32 antennas. • Generation of on-chip test vectors (PRN and “sky”) for testing w/o wafer inputs. • 2 chips, with 160 512 Mbps DDR 1.8 V interconnects provide full cross-bar capability for sub-array flexibility. • Phasing logic for 32 antennas, 1 sub-band…not yet implemented but S60 device believed large enough. • Diff signal DC bias established with single-ended 1k pullup resistor to 1.2 VDC at ERNI connector. Not enough room for 2 resistors. Input DC leakage current is low enough for satisfactory operation. • Implemented in Altera EP2S60F672C4 FPGA (52% util w/o phasing logic) ~270 Gbps I/O. Input jitter tolerance Stratix-II, 0.44 UI (430 psec) minimum. EVLA Correlator CDR - Baseline Board

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  11. EVLA Correlator CDR - Baseline Board

  12. EVLA Correlator CDR - Baseline Board

  13. RXP FPGA • Test status: • Fully tested for core functionality…still need to add phasing logic. • Meets all core performance and functional goals. • PD ~6 W. • Fall back positions if phasing logic does not fit in one device (in increasing order of severity). • Split into 2 devices, with final sum in GigE FPGA. • Simple summation with 64 MHz max, and phase rotation on SB Stage 2 filter. • Use Phasing Board in baseline rack for original spec. EVLA Correlator CDR - Baseline Board

  14. RXP FPGA • Key tests • Receivers synchronize with no errors with long cable (6.5 m to 8 m) of varying grades, driven by LVDS drivers with no pre-emphasis. Tests ran for 2 Friday-to-Monday weekends. • ~2 x 1015 bits with no errors. • In final system, max cable length is 7 m, with higher-amplitude drivers with programmable pre-emphasis. • Want to try with more boards…but front panel fabrication delays!!! • DDR I/O, no errors over long term. Use 12 mA drivers, Altera tools say good for 622 Mbps with calculated capacitive loading. • Output eye to 1:2 buffers and Recirc FPGAs is ok. • Speed margin test, ok to >285 MHz (1.14 Gbps) EVLA Correlator CDR - Baseline Board

  15. RXP FPGA • LVDS test signal eye into 8 m of 700369 cable, measured at cable header, after equalization network (built into cable header). EVLA Correlator CDR - Baseline Board

  16. RXP FPGA • Test signal, 1.024 Gbps eye, after 8 m 700369 cable, measured at cable header. Diff threshold spec for Stratix-II is 200 mV. 0.56 UI = 546 psec. EVLA Correlator CDR - Baseline Board

  17. RXP FPGA • Test signal, 1.024 Gbps eye, after 8 m 700369 cable, measured at PCB RXP vias. EVLA Correlator CDR - Baseline Board

  18. RXP FPGA • 1.024 Gbps LVDS output eye, measured at 1:2 buffer input. EVLA Correlator CDR - Baseline Board

  19. RXP FPGA • 512 Mbps DDR tx eye, at tx vias (most points not accessible—buried vias—for best SI). EVLA Correlator CDR - Baseline Board

  20. Recirculation FPGA • Receives 8 x 1.024 Gbps DATA, and 4 x 1.024 Gbps CTRL lines. • Synchronizes, decodes, and formats data for transmission to corr chip array. • Includes, phase generation, dumptrig decode, timestamp generation, recirculation functions, cross-bar switching, testing. • Generates 8 separate phase-controlled clocks for corr chip array. • Y Recirc FPGA re-times and transmits data for the next board in the daisy chain. • Implemented in Altera EP2S30F672C4 FPGA (39% util); S30 used for internal RAM capacity. EVLA Correlator CDR - Baseline Board

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  22. EVLA Correlator CDR - Baseline Board

  23. EVLA Correlator CDR - Baseline Board

  24. Recirc FPGA • Test status: • No errors/anomalies over months of testing. • Meets core functionality and performance requirements. • Some internal FPGA refinement of Y LVDS tx topology and reduction of 2.5 V I/O switching current for best noise immunity/lower jitter. • PD ~3.5 W, including I/O. EVLA Correlator CDR - Baseline Board

  25. Recirc FPGA • Key tests: • 24 hour test running data thru external and internal recirc DPSRAM and capturing correlation coefficients—no comparison errors. • Also run with Recirc-to-corr chip testvectors…no errors. • Y Recirc FPGA using 4 mA drivers to corr chip, with no errors. • OTS testing as well as test vector testing producing consistent and correct results. Dynamic recirculation functioning as designed. • Signal integrity all ok. • Y7 LVDS out, thru Patch Board to receivers in next board ok. • Can still use “Hypertransport” levels for more margin. • Y7 LVDS out, thru 6.5-8 m cable: receivers ok(!). • Speed margin test, operation >285 MHz (RXP-to-Recirc only tested). • Still need to test more boards. EVLA Correlator CDR - Baseline Board

  26. Recirc FPGA • LVDS eyes into X7 and Y7 FPGA, measured at Rx vias. • Receiver input capacitance and via to on-chip term evident. EVLA Correlator CDR - Baseline Board

  27. Recirc FPGA • Y7 tx eye, measured after Patch Board with 100 ohm wafer (resistor) termination (618 psec eye, 200 mV thresh.) 1.024 Gbps 1.140 Gbps EVLA Correlator CDR - Baseline Board

  28. Correlator Chip (ASIC) • Receives 90 ‘X’ and 90 ‘Y’ signals: • 8 x DATA, 4-bits each. • 8 x PHASE, 4-bits each. • Dvalid x 8, SE_CLK x 8, dump control (10), 1 x 32 MHz clock. • Complex-lag cross-correlation (2048 c-lags). • Full PT 4-bit multiplier. • Lag-based 3-level phase rotator. • 23-bit I and Q accumulators, no truncation. • 16, 128 c-lag sections which can be connected in various ways. • No CPU interaction for handling output data. • Implemented in 130 nm CMOS, 4 Mgate, TSMC standard cell. EVLA Correlator CDR - Baseline Board

  29. EVLA Correlator CDR - Baseline Board

  30. EVLA Correlator CDR - Baseline Board

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  36. EVLA Correlator CDR - Baseline Board

  37. EVLA Correlator CDR - Baseline Board

  38. Correlator Chip • Test status: • Fully tested, JEDEC qual testing, production units screened and tested. • Bit exact comparison with reference software correlator. • 2.6 W nominal power dissipation, 1.02 V, 256 MHz, Gaussian noise vectors. • 4.1 W worst case power dissipation, 1.2 V, pathological test vectors. • Exhaustive testing, including OTS testing at the VLA, has not produced even a hint of a problem (hang, anomaly etc.) • Only wrinkle is on-chip PLL sensitivity to SE_CLK; output clock to LTA and output signals have ~1.2 nsec jitter. This was fixed with low-jitter, 125 psec phase-step resolution clock provided by Recirc FPGA, so jitter does not accumulate. ~6 phase steps are error free. Also, LTA uses 128 MHz clock raw without PLL. EVLA Correlator CDR - Baseline Board

  39. Correlator Chip • Typical corr chip output eye. EVLA Correlator CDR - Baseline Board

  40. Correlator Chip • 128 MHz clock to LTA under worst-case jitter conditions. EVLA Correlator CDR - Baseline Board

  41. Correlator Chip • Rear view; decoupling, PCB stacked capacitor for Vcore EVLA Correlator CDR - Baseline Board

  42. LTA FPGA • Captures lag frames from correlator chip. • Accumulate in external 512 Mbit DDR SDRAM. • Fetch complete frames from RAM, and transmit to GigE FPGA on request. • Supports forced or inherent burst mode. • Do not allow corrupted data to go out unflagged. • The only exception is there is no LTA accumulation overflow bit. • Smallest FPGA, but probably the most complex design on the board. • Implemented in Altera Cyclone EP1C12F256C6 FPGA (52% util) EVLA Correlator CDR - Baseline Board

  43. EVLA Correlator CDR - Baseline Board

  44. EVLA Correlator CDR - Baseline Board

  45. EVLA Correlator CDR - Baseline Board

  46. LTA FPGA • Test status: • All SI checks ok. • No hangs, crashes, or hiccups. • Currently, accumulation runs at 125 MHz. • At least 128 MHz is required to meet recirculation “no data loss” goals (200 usec integration times). Can’t use 128 MHz clock because too much jitter. • GigE FPGA currently feeds a 31.25 MHz clock to it, with GigE FPGA re-design, will feed a 33.25 MHz clock, for 133 MHz accumulation (the limit of the FPGA DDR SDRAM IP core). • Some row 7 chips getting SER_CMD errs…FPGA code fix for auto-DDR edge selection based on SER_CMD only. • ~1.1 W power dissipation. EVLA Correlator CDR - Baseline Board

  47. LTA FPGA • DDRSDRAM typical DATA eye. EVLA Correlator CDR - Baseline Board

  48. GigE FPGA • Talk to each LTA using chip selects and simple serial command/response protocol. • Transfer frames, build into UDP/IP header, transmit on GigE to SFP (or XAUI to XPAK). • Design enhancements required to support phased data frames from the RXP FPGA. • Can route packets to SFP2 (normal) or SFP1 (CBE data capture). • Re-design, re-structure (for easier upgrade to 10G), and simplify the chip. EVLA Correlator CDR - Baseline Board

  49. EVLA Correlator CDR - Baseline Board

  50. GigE FPGA—Current Design EVLA Correlator CDR - Baseline Board

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