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FPGA Configuration and Firmware Development Updates for L1, L2, and L3 Trigger Systems

Overview of FPGA configurations and firmware development progress for the L1, L2, and L3 trigger systems. Includes milestones reached and upcoming tasks for synchronization, trigger generation, and data processing.

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FPGA Configuration and Firmware Development Updates for L1, L2, and L3 Trigger Systems

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  1. d0server1.fnal.gov/users/levan/ upgrade/L1General/CTPT_DFE_FPGAs.xls DFES will have 2 (or 1) XCV1000E, so need to order: 22 including a spare board CPSS : 1 XCV600, total of 4. STOV & STSX : 1 XCV600 each, total of 12. Need: 22 XCV1000E’s & 16 XCV600’s.

  2. L1 CFT/CPSax hit/occupancy — now ! • Link Test Firmware • DFEA hit/occ firmware • Surrogate CTOT hit/occ firmware with L1FE (synchronization of inputs and L1L3 Sending) • Waiting for hardware on the platform • L1 FPS full triggers — done ! • Need to implement synchronization and L1 L3 Sender a la CFT/CPSax (will take no time) • L1 CFT/CPSax full triggers — mid/end July • Tracks, clusters, track/cluster association • L1 pipeline, isol. tracks, double tracks, … (?) • L2 CFT/CPSax — end of July, mid-August • Synchronization of L2 records different? • L2L3 Sending (TrigSim)  Trigger Examines • L2 CPSst— end of July • Decided on FPGA configurations, DFES Ok • Need to start with CPSS soon! • L2 FPS— September • — matching to avoid truncation (TrigSim)? • L2 STOV/STSX— mid/late fall

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