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What Makes a Design Difficult to Route

What Makes a Design Difficult to Route. Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo Tellez Presented by Zhicheng Wei. What Makes a Design Difficult to Route. INTRODUCTION AND BACKGROUNDS COMMON CONGESTION METRICS GLOBAL ROUTING CONSTRAINTS

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What Makes a Design Difficult to Route

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  1. What Makes a Design Difficult to Route Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo Tellez Presented by Zhicheng Wei

  2. What Makes a Design Difficult to Route • INTRODUCTION AND BACKGROUNDS • COMMON CONGESTION METRICS • GLOBAL ROUTING CONSTRAINTS • DETAILED ROUTING CONSTRAINTS • PLACEMENT TECHNIQUES • LOGIC SYNTHESIS TECHNIQUES • REPEATER INSERTION TECHNIQUES • CONCLUSION

  3. What Makes a Design Difficult to Route • INTRODUCTION • Modern technology requires complex wire spacing rules and constraints • High performance routing requires multiple wire width (even same layer) • Local problems including via spacing rules, switchbox inefficiency, intra-gcell routing All of these problems make routing hard to model and lead to huge congestion issues!

  4. What Makes a Design Difficult to Route • BACKGROUNDS • Routing problems should be considered in 3D instead of 2D • Meet congestion constraints during global routing • Try to satisfy capacity in detailed routing with a given global routing solution • Over-the-cell routing breaks traditional channel/switchbox model

  5. What Makes a Design Difficult to Route • COMMON CONGESTION METRICS • Total Overflow • Average worst X% average worst 20% routing edges below 80% is routable • Total routed wirelength (RWL) significantly above Steiner tree may indicate routing difficulties • Number of scenic nets wirlelength/minimum Steiner tree length ratio > 1.3 is generally considered scenic • Number of nets over X% nets passing through gcells whose congestion is over X% • Number of violations • Routing runtimes

  6. What Makes a Design Difficult to Route • COMMON CONGESTION METRICS • Total Overflow

  7. What Makes a Design Difficult to Route GLOBAL ROUTING CONSTRAINTS • Choice of gcell size • gcell size too small large global routing space and takes more time to route • gcell size too large not able to expose congestion problems and shift burden to detail routing • Handling scenic nets • go very scenic = bad timing performance • impose scenic constrains on the router

  8. What Makes a Design Difficult to Route DETAILED ROUTING CONSTRAINTS • Prediction failure in global routing hot sports predicted by global routing may not be open and shorts in detailed routing

  9. What Makes a Design Difficult to Route DETAILED ROUTING CONSTRAINTS • Pin access problem certain configurations make accessing pin from higher metal layer impossible • Via modeling challenge Vias do not scale as well as device at each technology node Vias serve as routing blockages which impact local congestion Via modeling becomes non-trivial, esp with different metal pitches

  10. What Makes a Design Difficult to Route PLACEMENT TECHNIQUES Congestion caused by time-driven placement

  11. What Makes a Design Difficult to Route PLACEMENT TECHNIQUES Modern placement focus on minimization of HPWL Uniform placement does not always work! Uniform placement does not mean uniform wire spreading! Consider congestion-driven placement

  12. What Makes a Design Difficult to Route PLACEMENT TECHNIQUES • Congestion Reduction by Iterated Spreading Placement (CRISP) • Selectively spreading the placement in regions with high global congestion

  13. What Makes a Design Difficult to Route LOGIC SYNTHESIS TECHNIQUES • Logic synthesis generally ignores placement information • Create structures good for timing closure but bad for routing • Logic synthesis transforms to alleviate local congestions identify logic fan-in tree which is physically wirelength inefficient rebuild logic tree and place new synthesized gates wirelength is minimized and congestion alleviated

  14. What Makes a Design Difficult to Route REPEATER INSERTION TECHNIQUES • Repeaters are inserted to meet timing constraints Divide long wires into small segments • Layer assignment Obtain enormous speed advantage using thick metal for most critical paths • Routing congestions caused Corona effect (congestion around corner of blockages) Aggressive layer promotion (fewer resources at higher metal layer)

  15. What Makes a Design Difficult to Route Aggressive Layer Promotion

  16. What Makes a Design Difficult to Route Corona Effect

  17. What Makes a Design Difficult to Route CONCLUSION • Physical synthesis issues in placement, global/detail routing, logic synthesis • Advanced technologies require more complicated modeling plan • Capture more detailed routing effects in global routing stage • Estimation techniques need to be fast to optimize routing fast

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