Introduction to IC Test

Introduction to IC Test Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/04/26

Bonus Project 1 • Write a set of C (or C++) programs to read the ISCAS85 benchmark. • Construct an internal model (data structure). • Do functional logic simulation in the internal model. • Add a bit for fault insertion in each gate and do serial fault simulation.

Example for Proj#1/ (1) ISCAS85 Benchmark TDL Example MODULE : C17; INPUTS : I1gat, I2gat, I3gat, I6gat, I7gat; OUTPUTS : I22gat, I23gat; DESCRIPTION : TDL file created by Carafe of Hemlock USE : DEFINE : aoi21s_0(q=I7) = aoi21s(a1=I10,a2=I7gat,b=I13); ai2s_3(q=I10) = ai2s(a=I3gat,b=I6gat); ai2s_2(q=I22gat) = ai2s(a=I8,b=I12); i1s_1(q=I23gat) = i1s(a=I7); i1s_0(q=I13) = i1s(a=I12); ai2s_1(q=I12) = ai2s(a=I2gat,b=I10); ai2s_0(q=I8) = ai2s(a=I1gat,b=I3gat); END : MODULE;

Example for Proj#1/ (2) ISCAS85 Benchmark Verilog Example module C17(I1gat, I2gat, I3gat, I6gat, I7gat); input I1gat, I2gat, I3gat, I6gat, I7gat; output I22gat, I23gat; wire I7, I8, I10, I12, I13; // ISCAS85 C17 Circuits in Verilog aoi21s aoi21s_0(.q(I7), .a1(I10), .a2(I7gat), .b(I13)); ai2s ai2s_3 (.q(I10), .a(I3gat), .b(I6gat)); ai2s ai2s_2 (.q(I22gat), .a(I8), .b(I12)); ils ils_1 (.q(I23gat), .a(I7)); ils i1s_0 (.q(I13), .a(I12)); ai2s ai2s_1 (.q(I12), .a(I2gat), .b(I10)); ai2s ai2s_0 (.q(I8), .a(I1gat), .b(I3gat)); endmodule;

Example for Proj#1/ (3) TDL Parser and Internal Model #include <stdio.h> #include <stdlib.h> #include <string.h> #include <alloc.h> #define CALLOC(n,x) ((x *)calloc(n,sizeof(x))) typedef struct line_struct LineType; struct line_struct { char *line, id[10], ip[6][10]; int im; /* max input lead */ char valid; int level; LineType *next; }; LineType *Head, *Tail; /* Head and Tail of */ typedef struct IDNode IDnode; struct IDNode { char *id; IDnode *next; }; IDnode *I[10000];

Example for Proj#1/ (4) TDL Parser and Internal Model main(argc, argv) int argc; char *argv[]; { FILE *tdlf; char firstname_tdl[20], str[100],s[30],*tok,*temp, ok, Y, F; LineType *t,*p,*q; int i; if(argc != 2) {printf("Usage: tdlr file<.tdl>\n"); exit(0);} strcpy(firstname_tdl,argv[1]); strcat(firstname_tdl,".tdl"); if((tdlf=fopen(firstname_tdl,"r"))==NULL) { printf("Open file error!\n"); exit(1);} do{ fgets(str,100,tdlf); printf("%s",str); sscanf(str,"%s ",s); }while( strcmp(s,"MODULE") ); do{ fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); }while(strcmp(tok,"INPUTS"));

Example for Proj#1/ (5) TDL Parser and Internal Model fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); Head=Tail=NULL; while(strcmp(tok,"OUTPUTS")){ t=CALLOC(1,LineType); t->im=0; t->valid=1; t->level=0; t->next=NULL; strcpy(t->id,tok); if(Head==NULL) Head=Tail=t; else {Tail->next=t; Tail=t;} fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); }

Example for Proj#1/ (6) TDL Parser and Internal Model fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); while(strcmp(tok,"DESCRIPTION")){ fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); } do{ fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); }while(strcmp(tok,"DEFINE")); fgets(str,100,tdlf); temp=((char *)calloc(1,strlen(str)+1)); strcpy(temp,str); tok=strtok(str,"(=: ");

Example for Proj#1/ (7) TDL Parser and Internal Model while(strcmp(tok,"END")){ t=CALLOC(1,LineType); t->next=NULL; t->im= t->valid=t->level=0; t->line=temp; tok=strtok(NULL,"=)"); tok=strtok(NULL,"=)"); strcpy(t->id,tok); tok=strtok(NULL,"("); tok=strtok(NULL,",); "); while(tok!=NULL) { if(tok[0]==')'||tok[0]==';'||tok[0]=='\n') break; strcpy(t->ip[t->im++],tok); tok=strtok(NULL,",); "); } Tail->next=t; Tail=Tail->next; fgets(str,100,tdlf); temp=((char *)calloc(1,strlen(str)+1)); strcpy(temp,str); tok=strtok(str,"(=: "); } }

Bonus Project 2 • Be familiar with a test tool in this laboratory environment, say, SynTest, Mentor or Synopsys, e.t.c. • Try at least 3 instances in ISCAS89 benchmark, do the full-scan test syntheses and obtain the test patterns and report the associated parameters (i.e., fault coverage, test efficiency and approximated area overhead.)

Syllabus & Chapter Precedence Introduction Modeling Logic Simulation Fault Modeling Fault Simulation Testing for Single Stuck Faults Design for Testability Test Compression Built-In Self-Test (II)

Testing for Single Stuck Faults • Test Generation: Random vs. Diterministic • ATPG for SSFs in Combinational Circuits • ATPG for SSFs in Sequential Circuits

Test Generation: Random vs. Deterministic Fault Selection Test Selection Test Generation Fault Simulation Fault Simulation Fault Dropping Fault Dropping No No TE enough? TE enough? Done Done

Test Generation: Random vs. Deterministic Test Efficiency Expected time per pattern 0 #patterns 0 Test set generation time

5-Value Operations AND 0 1 D X 0 0 0 0 0 0 0 0 1 0 1 D X D 0 D D 0 X X 0 0 D D D D D D D D D D X 0 X X X X OR 0 1 D X 0 0 1 D X 1 1 1 1 1 1 1 D D 1 D 1 X 1 1 X X X 1 X X X Notations

Test Generation for Fanout-Free Tree 3. Propagate(l, v/vf ) 2. Justify(l, ~v) 1. Set all values to X Justify for Enabling X X X X X X X X X X X X X X

Decision Process in Justification 1 1 1 State 1 1 State 2

Decision Process in Justification 000 001 010 011 100 101 110 State 1 0 Branches of Decision Tree

Backtracking in Decision Tree B B C C Sub- Process Conflict or Contradiction A In typical circuits, test generation for some faults usually have more than thousands of backtracking

Possible Backtracking with Fanout Test Generation for Fanout-Free Tree Backtracking 3. Propagate(l, v/vf ) 2. Justify(l, ~v) 1. Set all values to X Justify for Enabling X X If Conflict? X X X X X X X X X X X X

Concept of Frontiers J-frontier: all gates keeping track of unsolved D-frontier: all gates with any D or \D on their inputs – a queue waiting for propagation. J-Frontier D-Frontier

Basic Test Generation Algorithm TG() { if( imply_and_check( ) ) { if ( error_at_PO and all_lines_justified ) return(1); if ( no error can be propagated to a PO) return(0); select an unsolved problem; for (all ways) { select a untried way to solve it; if (TG( ) ) return (1); } } else return(0); }

Implication Process • Purposes • Compute all values that can be uniquely determined by implication. • Check for consistency and assign values. • Maintain the D-frontier and the J-frontier. • Operations • Imply_and_check() retrieves in tern every entry in the assignment queue (like the time wheel in logic simulation).

Backward Implication 1 0 x x x 1 1 1 x x 1 x 1 x 1 x g 1 0 J-frontier ← J-frontier U {g} 1 0

Forward Implication: Binary Values 0 x 0 1 x 1 x 1 0 0 1 0 g g x 0 x J-frontier ← J-frontier \ {g} J-frontier ← J-frontier \ {g} 1 E x 0 x 0 g g E E D-frontier ← D-frontier \ {g} D-frontier ← D-frontier \ {g}

Forward Implication: Error Values E E E x g E x 1 g x E E x D-frontier ← D-frontier U {g} g E D-frontier ← D-frontier \ {g} E x 0 E x g E g x 1 D-frontier ← D-frontier \ {g} D-frontier ← { } Unique Drive

D-Algorithm Roth 1966 D_Algo() { if imply_and_check() if(error not at PO){ repeat{ select(g, D_frontier); enabling(g); if(D_algo()) return(SUCCESS); } until(all gates tried) return(FAILURE); } if(J_frontier) repeat{ select(g, J_frontier); select(input, g); select(input j, g); controlling(j, g); if(D_algo()) return(SUCCESS); enabling(j, g); } until(all gates tried); else return(SUCCESS); return(FAILURE); } Characteristic feature: Multiple-path sensitization, ability to propagate errors on several reconvergent paths.

Variety of PG Algorithms Speeding Skills Dynamic/static learning Single (PODEM) 5V 9V Multiple (D-algo) #values Sensitization or Desensitization ? #Paths

Example for D-Algorithm Schneider’s Circuit, 1967 h l j d’ e’ f’ d e f m k i n b g a c 1 0 0 1 1 0 1 1 1 1 1 1 J-frontier:________________ D-frontier:________________ g i k m n

Introduction to IC Test