Flex cable feasibility study : Context / Objectives

1. MISTRAL & ASTRAL SensorsFlex feasibility studyGilles CLAUS (on behalf of PICSEL-ALICE team of IPHC-Strasbourg)

2. 270 mm > 15 mm Flex cable feasibility study : Context / Objectives • Goal of this study  Based on STAR-PXL flex cable (proven technology) • Estimate minimum achievable cable width • Calculate voltage drop along the power bus • Calculate material budget • Design decisions for evaluation • Cable length for 9 chips ( 15 mm x 30 mm ) 9 x 30 mm = 270 mm • Cable width  15 mm + Bonding area ? mm (pads, bonding wire loop, decoupling capacitors) • Cable design done on FR4 by C.Illinger • GND & VDD traces  7 mm width – 30 µm Aluminium IPHC gilles.claus@iphc.cnrs.fr

3. Flex cable feasibility study : Minimum cable width • Minimum cable width : Study done by M.Goffe & IPHC µTechnique Team (M.Imhoff & Co) • 50 µm thick sensors • Wedge bonding • Minimum bonding pads distance : Chip  Flex • 500 µm  Loop too short • 800 µm  Acceptable value for bonding reliability • Result ~ 1 mm  Cable width ~ 16 mm • Better result achievable ? 800 µm 500 µm 500 µm IPHC gilles.claus@iphc.cnrs.fr

4. ΔU / segment 2 ΔU / segment 1 ΔU / segment 9 9 x I I 8 x I 2 x I Chip No 1 Chip No 9 Chip No 3 Chip No 2 One segment Flex cable feasibility study : Voltage drop • Calculation hypothesis • Common GND & VDD traces for analogue & digital • Aluminium traces : 7 mm width – 30 µm thick – ρ Al = 26.10-9 ohm.m • Sensors : 15 x 30 mm² - Power supply = 1,8 V • MISTRAL : Pd = 200 mW/cm²  I = 0,5 A/Chip - ASTRAL : Pd = 85 mW/cm²  I = 0,21 A/Chip • Voltage drop  MUST be <= 200 mV • Distance between two sensors = “One segment” • ρ Al = 26.10-9 ohm.m – Trace 7 mm width - 30 µm thick  R = 3,7 m ohm • Total voltage drop • ΔV1 = R x I, ΔV2 = R x 2 x I … ΔV9 = R x 9 x I  Arithmetic serie • Voltage drop = Sum of the serie = 9 x ( ΔV1 + ΔV9) / 2 = 9 x (RI + 9RI) / 2 = 45 x R x I Chip • MISTRAL (Pd = 200 mW/cm²  I = 0,5 A/Chip) • ΔV = 45 x R x I Chip = 45 x 0,0037 x 0,5 = 83 mV  Total (Vdd, gnd) = 166 mV • ASTRAL (Pd = 85 mW/cm²  I = 0,21 A/Chip) • ΔV = 45 x R x I Chip = 45 x 0,0037 x 0,21 = 35 mV  Total (Vdd, gnd) = 70 mV IPHC gilles.claus@iphc.cnrs.fr

5. Flex cable feasibility study : Voltage drop • Remark • Voltage drop calculation done in DC • This true ONLY if there is enough decoupling capacitors / chip on the flex • If it’s not the case  There is an AC component  I power bus = I dc + I ac • At which freauency ? • Clock and harmonics  Input 40 MHz – Serializer 600 MHz – 1,2 GHz (1,2 Gb/s – 2,4 Gb/s)  AC component if unbalanced currents (should be minimized with differential architecture - LVDS) • At frames frequency : T r.o = 20,8 µs  F = 100 KHz  No risk with skin effect BUT Low frequency requires high capacity value • What’s about skin effect ? • Gianluca’s Talk yesterday  Aluminium 12 µm @ 50 MHz < 1 / 2 Trace thickness (35 µs) • Which effect is more critical : Traces inductance / Skin effect ? • Is there simulations ? • Chip current profile ? IPHC gilles.claus@iphc.cnrs.fr

6. Flex cable feasibility study : Material budget • Radiation length • Kapton flex 50 µm Xo = 34,2 cm  X = 0,0146 % Xo • 2 x Aluminium 30 µm X0 = 8,897 cm  X = 2 x 0,037 % Xo = 0,074 % Xo • 2 x Adhesive 25 µm Xo = 33,8 cm  X = 2 x 0,0074 % Xo = 0,0148 % Xo • Total X = 0,1 % Xo • Total thickness = 160 µm Al 30 µm Adhesive 25 µm Kapton 50 µm Adhesive 25 µm Al 30 µm IPHC gilles.claus@iphc.cnrs.fr

7. Flex cable feasibility study : Conclusion • Flex • Does it makes sense to continue this study ? • Now it’s a design in a CAD tools  Nothing has been produced • Is there manpower to pursue this study ? • Power distribution – Voltage drop • Definition of minimum decoupling capacitors value / chip • Skin effect / Traces inductance • Chip current profile IPHC gilles.claus@iphc.cnrs.fr

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