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Lecture 0. Course Introduction

COM506 Computer Design. Lecture 0. Course Introduction. Prof. Taeweon Suh Computer Science Education Korea University. Course Information. Instructor Prof. Taeweon Suh References Digital Design and Computer Architecture by David Money Harris and Sarah L. Harris, Morgan Kaufmann, 2007

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Lecture 0. Course Introduction

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  1. COM506 Computer Design Lecture 0. Course Introduction Prof. Taeweon Suh Computer Science Education Korea University

  2. Course Information • Instructor • Prof. TaeweonSuh • References • Digital Design and Computer Architecture by David Money Harris and Sarah L. Harris, Morgan Kaufmann, 2007 • Computer Organization and Design by David Patterson and John Hennessy, 4th Ed., Morgan Kaufmann, 2009 (No Korean-translated version) • Computer Architecture: A Quantitative Approach (Fourth Edition) by John L. Hennessy and David A. Patterson, 2007, Morgan Kaufmann • Web materials at http://www.adc.co.kr • Prerequisites • COMP212 Computer Architecture • COMP211 Computer Logic Design • C language • Verilog-HDL • Office hours • After class as needed • By appointment at Lyceum 307 • Contact Information • suhtw@korea.ac.kr • 02-3290-2397 • Class web page • http://esca.korea.ac.kr/

  3. Undergrad-level Computer Architecture • Topics covered include the followings • RISC ISA (Instruction Set Architecture) • MIPS, ARM • In-order microarchitecture • Single-cycle MIPS • Pipelined (5-stage) MIPS • Memory hierarchy • Registers, caches, main memory, and HDD • Virtual memory • TLB (Translation Lookaside Buffer) http://www.mips.com/ http://www.arm.com/

  4. Graduate-level Computer Architecture • Topics include the state-of-art technologies to increase performance in modern computers • Out-of-order microarchitecture • ILP (Instruction-level Parallelism) • Limits on ILP • TLP (Thread-level Parallelism) • Multi-core and multiprocessors • Cache coherence protocols • Advanced topics in memory hierarchy

  5. COM506 Computer Design • Gain practical knowledge of CPU design • Experiment with Lucida • 32-bit 5-stage RISC processor • 16-bit instructions (like Thumb mode in ARM) • Adchips calls it an EISC (Expandable Instruction Set Computer) architecture • http://www.adc.co.kr • Analysis of CPU source code written in Verilog-HDL • Simulation & FPGA-based emulation • Lucida RTL change and verification for performance improvement • Branch predictor • Instruction queue w/ multi-cycle cache access • Load/store queue

  6. COM506 Computer Design (Cont) • Seminar & Discussion-based • Not a lecture-based course • Environment & Tools • Windows or Linux-based • Simulations: ModelSim-XE (Xilinx Edition), ISE, Verilog-XL(?) • Emulation: Virtex-5 or Virtex-6

  7. Grading Policy • No exams • RTL Analysis & Presentation: 30% • Term Project: 50% • Branch predictor (?) RTL coding & Validation • Active Class Participation: 20%

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