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IEEE BTW 2008 Workshop September, 2008 Fort Collins, Colorado Presented by: Alan Albee Teradyne ICT Product Manager. Next Generation ICT Testing Challenges. Next Generation ICT Challenges. Changing Technologies, Testing Philosophies, and Economic conditions….

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IEEE BTW 2008 Workshop

September, 2008

Fort Collins, Colorado

Presented by: Alan Albee

Teradyne ICT Product Manager

Next Generation ICT Testing Challenges

next generation ict challenges
Next Generation ICT Challenges

Changing Technologies, Testing Philosophies, and Economic conditions…

  • Diverse ICT Manufacturing Requirements
    • High performance vs “Just-Enough-Test” systems
  • Ultra-low voltage technologies
    • How to test reliably and safely
  • Shrinking package geometries
    • How to maintain acceptable fault coverage with Vectorless Test techniques
  • High Density Interconnect designs
    • How to maintain acceptable fault coverage without physical test access
  • Proliferating boundary scan and DFT technologies
    • How can ICT best take advantage of these PCB testability features
  • Skill levels of test developers and operators
    • How do you improve user productivity of test developers and operators
  • Increasing test throughput requirements
    • How to keep up with increasing Assembly Equipment speeds and eliminate test bottlenecks

ICT Test Challenge:

Diverse ICT Requirements

differing demands on ict testers
Differing Demands on ICT Testers…
  • Low margin manufacturers demand low cost
  • Untrained operators demand simple and easy to use operation
  • Highly skilled test engineers demand powerful programming capabilities
  • High reliability product manufacturers demand high fault coverage and safe testing
  • High volume manufacturers demand ever higher test throughputs
  • Outsourcing business models demand turnkey solutions and equipment compatibility
  • Complex PCB Manufacturers demanding high pincount capacity systems
  • Different market segments and regions implementing different test philosophies
historical bed of nails electrical test alternatives
Historical Bed-Of-Nails Electrical Test Alternatives


High Performance ICT


Fault Coverage

Standard In-Circuit Testers

Manufacturing Defect Analyzers








teradyne s scalable ict product platform strategy

Pure Hybrid


Analog Only

Teradyne’s Scalable ICT Product Platform Strategy



TestStation LX

Pin Count

Pin Capacity

Common Instruments and Options

Common Software Environment

Common Technologies

selectable pin board options
Selectable Pin Board Options

Multiple pin board options to match manufacturer’s pin count, technology, and budget requirements…

scalable hardware features
Scalable Hardware Features

Add these capabilities as needed…

  • Clock/Sync/Trigger VLSI test capabilities
    • Advanced digital device testing and timing control
  • Backdrive measurement and high accuracy features
    • Increased accuracy and safety when testing low-voltage parts
  • System frequency test module
    • Frequency and time event measurements
  • Power supplies
    • Up to 14 programmable and three fixed user supplies
  • Deep serial memory module
    • Enhanced performance of FLASH/ISP/BSCAN tests
  • Analog functional test module
    • Complex analog and mixed signal device testing
  • Custom function board
    • Vehicle control interface for automotive protocols
    • Integration of custom and third-party test application circuitry
scalable ict platform goal

Fault Coverage

Unpowered Analog



Analog comp values

Vectorless Test

Opens on digital pins and connector pins

Misoriented components

Powered Analog



Analog functional

BSCAN Instrument

BSCAN components

PLD programming

Digital Vectors

Fast detection of open digital pins

Missing / wrong digital components

Faults on mixed BSCAN / conventional nets

Scalable ICT Platform Goal
  • Buy only the test capability you need
  • Grow or reduce fault coverage without changing the tester
  • No need to change programs and test fixtures
  • No need to learn different test systems


ICT ++



< $100K


ICT Test Challenge:

Ultra Low Voltage Technologies

low voltage challenge for ict
‘Low Voltage’ Challenge For ICT...
  • Multiple voltage levels per IC
  • More susceptible to damage from ‘over-voltage’ spikes
  • More susceptible to damage from current ‘over-driving’
  • I/O logic levels are differentiated by milli-volts
    • Logic drivers & sensors must resolve to milli-volts levels
    • Voltage instability must not trigger logic transitions even under variable load conditions

Source of device stress and potential damage

Sourceof unstable tests & high false fails

newer parts are more sensitive to over voltage conditions
Newer Parts Are More Sensitive to Over-Voltage Conditions

Overvoltage conditions must be controlled

  • Today’s processors have strict over-voltage/time specification
  • AGTL signals should never exceed 1.8V
  • Should not exceed 1.5V for >10nsec
  • Must ensure voltages remain in Safe Operating Region

Source : Intel Corp. Itanium 2 processor datasheet

studies prove that over voltage conditions destroy or damage parts





Studies Prove that Over-Voltage Conditions Destroy or Damage Parts

9V backdrive spike for 40nsec, 16V peak for 10nsec !

These spikes can occur without proper isolation

74LVT240A 3.3V.

Backdriven high then


Time to 63% Failure (sec)

Time to Failure (seconds)

11 7.3 5.5 4.4 3.6 3.1 2.7 2.4 2.2

Gate OxideVoltage (Volts)

Data taken from a study sponsored by the National Science Foundation and the Semiconductor Research Corporation

Graph Source : IEEE Transactions on Electron Devices, Vol 51, 08/2004

potential economic impact of using ict not designed for low voltage devices
Potential Economic Impact of Using ICT not designed for Low Voltage Devices












Fine Pitch


  • Reduced Fault Coverage
    • Unable to test components without violating device specifications
  • Increased False Failures
    • Needless replacement of good devices
    • Increased repair and re-test costs
    • Possible damage to product during the repair cycle
  • Damaged Components
    • Catastrophic or latent failures related to gate oxide breakdown, ESD protection diode over-stress or CMOS latchup
ict capabilities that teradyne designed into teststation to enable safe low voltage testing
ICT Capabilities that Teradyne Designed into TestStation to Enable Safe LowVoltage Testing
  • Accurate Driver/Sensors
    • Closed loop, low impedance pin
    • Guaranteed 15mV D/S accuracy
    • 2.3mV programming resolution
    • Real-time current measurement
    • Automatic driver verification
    • Programmable per-pin logic levels
    • Dual-level thresholds
  • Dedicated Digital Controller
    • Fast test throughput
    • Consistent and repeatable timing
    • Reduced backdrive duration
  • Test Software Controls
    • Multi-level digital isolation
    • Programmable backdrive controls
    • Backdrive measurement reports

ICT Test Challenge:

Shrinking Package Geometries

increasing reliance on vectorless test techniques to detect faults
Increasing Reliance on Vectorless Test Techniques to Detect Faults
  • ICT capacitive test technique that is used to detect open pins on components and connectors
  • Benefits
    • Does not require the PCBA to be Powered-Up
    • Fast implementation (Learn techniques do not require the creation of complex test vectors)
    • Precise pin-level diagnostics
  • Limitations
    • Requires extra fixture hardware
    • Slower test time
    • Does not verify that device functions correctly
    • Limitations detecting open power and ground pins
    • Internal ground planes can limit fault coverage
    • Small geometries reduce signal magnitudes, possibly making pins untestable or measurements unrepeatable
teradyne s 3 rd generation vectorless test solution framescan fx 2 0
Teradyne’s 3rd Generation Vectorless Test Solution – Framescan FX 2.0
  • Hardware and Software Enhancements
    • Redesigned multiplexer and amplifier hardware
    • Signal to noise ratio improvements of more than 20dbV
    • Conformally coated amplifier for better noise immunity
    • Includes advanced learn algorithms for setting test limits
  • Provides increased fault coverage
    • Improves test coverage on the smallest package technologies
    • Increased measurement sensitivity (5pA @9.5KHz)
  • Provides increased measurement stability
    • Improves pin threshold settings
    • Reduces risk of false calls on device pins
    • Enhances board to board consistency

ICT Test Challenge:

High Density PCB Designs

trends driving loss of physical access


Trends Driving Loss of Physical Access
  • Increasingly more complex bare boards (HDI)
  • Blind and buried vias, via in pad
    • 4 mil diameter finished holes
  • Track width and spacing decreasing
    • 3 mil lines 3 mil spacing 1 oz copper
    • 2 mil lines 2 mil spacing ½ oz copper
  • Less copper available on board surface for electrical test access
  • High Speed Busses
    • Nets cannot tolerate additional impedance of test pads
    • Differential signals double I/O pincount and reduce voltage swings
  • Serial DFT Protocols like BSCAN and CAN
    • Allow designers to remove test points
  • Increasing test fixture costs and complexity
    • Reduce costs with less probes


what loss of electrical test access means for ict
What Loss of Electrical Test Access Means for ICT...
  • Elimination of ICT as a viable test strategy for some products
    • Portable consumer products like cell phones, audio players, etc
  • Increased requirements for integrated reduced access tools
    • Boundary scan interconnect and virtual pin testing
    • Adaptive test generation
    • Indirect testing through serial resistors and buffers
    • Functional cluster testing
    • Sophisticated diagnostic algorithms
    • Combined boundary scan and vectorless test techniques
  • Increased need to complement ICT with other test techniques
    • AOI, AXI, and Functional test
    • BSCAN and BIST
    • Distributed Test Strategies
  • ICT systems configured for reduced test roles
    • Scalable ICT systems to match reduced test requirements
    • Ability to integrate easily with other 3rd party tools
teradyne limited access ict tools








Nail 2




Nail 1





Component under Test

Standard Nail

Values below 10K

Teradyne Limited Access ICT Tools

Digital Jumper

  • Scan Pathfinder
  • Digital Jumpers
  • Remote Drive / Sense
  • Indirect Vectorless Test
  • Cluster Testing
  • Functional Testing
  • Adaptive Test Generators
  • Combined BSCAN and Vectorless Test

Remote Drive

Nail 3

Remote Sense

combined bscan and vectorless test technique
Combined BSCAN and Vectorless Test Technique

Output Signal

Re-gain testability on

high speed signals

through virtual access






High Speed Signals

with no Test Pad Access

Low Noise ActiveBuffer

ProbePlate Sensor

Connector or non-BS IC


Boundary Scan BGA

Synchronous Digitizer

Test Access Port (TAP)



ATE Digital Drivers

test strategy analysis tool
Test Strategy Analysis Tool





PCB data

Compare coverages

and select final strategy

Export embedded strategy specific machine

files automatically

Define multiple


Implement Test Strategy

  • Models multiple test strategies
  • Objectively reports fault coverage
  • Supports test point reductions
  • Selects optimal test strategy

AOI Reflow AXI Prober ICT


ICT Test Challenge:

Increasing BSCAN and DFT

teradyne bscan survey findings
Teradyne BSCAN Survey Findings
  • Boundary scan designs are increasing
    • More boundary scan parts to choose from
    • No longer a price disadvantage to use them
    • Design tools support boundary scan
    • Viable reduced access test strategy
  • Boundary scan features are being used throughout the product life cycle
    • Design, Prototype, NPI, Production, Field Operation, and Service/Repair depot
  • Manufacturers are using many different boundary scan solutions
    • No clear market winner
    • They prefer to use the benchtop solution with which they are most familiar
    • General confidence that all solutions can perform standard boundary scan tests
    • Mixed feelings regarding how to use boundary scan at ICT
  • Features rated most important in a good boundary scan solution
    • Vector Portability
    • ATPG software and Debug Tools
    • Diagnostic Accuracy
    • ICT/MDA Integration
    • Cost
teradyne s ict boundary scan strategy
Teradyne’s ICT Boundary Scan Strategy
  • Maintain native Teradyne 1149.1 BSCAN Solutions
    • BasicSCAN and Scan Pathfinder
    • For manufacturers who are not already using benchtop BSCAN solutions
    • For manufacturers who do not have a BSCAN test portability requirement
    • For manufacturers who do not want to add extra instruments or special fixture wiring
  • Collaborate with Popular Benchtop BSCAN Vendors
    • Provide “integration friendly” tester environment for Benchtop BSCAN solutions (Goepel, JTAG Technologies, Asset, Corelis, Acculogic)
    • For manufacturers who have BSCAN test requirements beyond 1149.1
    • For manufacturers who want to re-use boundary scan tests created in their engineering labs
fostering partnerships with 3 rd party bscan solutions
Fostering Partnerships with 3rd Party BSCAN Solutions

Integration Levels

  • Level 3: Product Available (from Bscan Vendor)
    • Goepel SFX Plug-In Card
      • Designed by Goepel with Teradyne’s support and cooperation
      • Introduced at Electronica in November 2006
    • JTAG Symphony 228X
      • Converts JTAG vectors to Teradyne test language – no JTAG instrumentation required
  • Level 2: Semi-Automated
    • JTAG Symphony 228X Plus
      • Incorporates JTAG instrumentation into TestStation for fast PLD programming
      • TestStation Hybrid Test Model available
    • Acculogic CFB Connection
      • TAP signals are routed through Teradyne CFB
  • Level 1: Application Note
    • Asset Intertech Scanworks
      • Application implemented at Mil/Aero and Storage manufacturers
    • Corelis ScanPlus
      • Application Note available on Support site

Integration and partnership activities are driven by customer opportunities

example 3 rd party bscan product solutions
Example 3rd Party Bscan Product Solutions
  • Goepel CFB plug-in card
    • Integrated on TestStation CFB
    • Allows re-use of Goepel bscan tests
    • Three versions supported with different capacity and pricing
  • Two JTAG Technologies Integration Options
    • CFM option for TestStation CFB
    • Test language converter using DSM
    • Allows re-use of JTAG bscan tests
    • Product name Symphony

ICT Testing Challenge:

Reduced Operator Skill Levels

ict operation challenges
ICT Operation Challenges
  • Manufacturing move to lower cost regions
    • Untrained test operators
    • High employee turnover
    • May only understand local language
  • Time to market pressures
    • Not enough time for training
    • Learn on the job
    • Difficulty using advanced features of the tester
    • Limited time to debug marginal tests or optimize fault coverage
    • Compromised fault coverage results

Need for program development and debug accelerators…

new operator user interfaces simplify and shorten typical ict debug and production activities
New Operator User Interfaces Simplify and Shorten Typical ICT Debug and Production Activities
  • Short learning curve
    • Easy access to debug and production tasks
    • Graphical editing of tests
    • Quick access to board data
    • Exposes powerful features of the tester
  • Charts reveal quality of test measurement
  • Linked CAD and schematic views
  • Optional performance meters
  • Local language capability
  • Flexible Limit modes prevents unauthorized operator changes
  • Standard Windows controls
  • “Classic” mode available for expert users
new user interfaces simplify vectorless test debug activities
New User Interfaces Simplify Vectorless Test Debug Activities
  • New User Interface simplifies Vectorless Test Debug Activities
  • Detailed measurement results for each pin
  • Point and click debug
  • No Test Language Required
automated tools measure and enhance test quality
Automated Tools Measure and Enhance Test Quality
  • Test Quality Tools
    • AutoDebug - Automatically debugs failing and marginal tests
    • AutoAdjust – Can automatically shift and/or widen test limits
    • Analyze (Allfault) – Reports fault coverage and test reliability
  • Customizable based on user defined quality criteria
    • User specifies metrics for both accuracy and stability per test type
    • Command file provides hands-off execution

ICT Test Challenge:

High Volume Test Requirements

challenges for high volume manufacturers
Challenges for High Volume Manufacturers
  • PCB assembly equipment speeds continue to increase
    • Manufacturing beat rates can be less than 30 seconds
  • In-circuit tester becomes bottleneck on manufacturing line
    • ICT test times limit the amount of boards that can be manufactured
  • Manufacturing facilities often have limited floor space
    • Adding additional test equipment is not always possible







Fine Pitch






program optimization tools can help
Program Optimization Tools Can Help…
  • Optimizes AC measurement parameters
  • Select fastest Shorts testing algorithm (linear or binary)
  • Reduces program Delay values
  • Optimizes expected values to minimize Instrument Autoranging
inline automated solutions can eliminate handling times
Inline Automated Solutions can Eliminate Handling Times

ICT instruments available as Rack Mount components for easy integration into automated handler systems

  • TestStation TSR Models
    • Tester Instruments available in 19” rack mount chassis
    • Power Controller Assembly
    • Integration Manual
  • Custom Configurations
    • Three receiver options
    • Selectable multiplexing
    • Vacuum or Press-Down
  • Automation partners
    • Nutek, IPTE, Hirata




other methods used to satisfy high volume test requirements and their drawbacks
Other Methods Used to Satisfy High Volume Test Requirements… and their Drawbacks
  • Add additional testers to the manufacturing line
    • Increases capital equipment, test fixture, and operation costs
    • Requires additional manufacturing floor space and test cells
  • Underutilize tester by removing tests
    • Reduced fault coverage
    • Extra program maintenance
  • Remove in-circuit test from manufacturing line
    • Implement less effective inspection strategy
    • Increased chance of shipping defective products








Fine Pitch





a new concurrent test solution
A New Concurrent Test Solution
  • Completely concurrent test operation
    • Supports simultaneous testing of two boards
    • All test techniques support parallel test
  • Twice the throughput of standard ICT testers
    • Doubles test throughput in the same footprint as single test system
  • Manual or automated versions
    • Easy integration into automated manufacturing lines
  • Significant cost savings
    • Less expensive equipment, fixture, and operation costs
concurrent test solution economic benefits
Concurrent Test Solution – Economic Benefits

Does not meet requirements

Duo solution saved manufacturer $176K and reduced cost per panel by $0.63


Teradyne Solution:

TestStation Test Platform


teradyne ict test platform summary
Teradyne ICT Test Platform Summary
  • Scalable ICT system design
    • Configurable from MDA+ to high performance / high pincount digital
  • New Driver/Sensor Pin Electronics
    • For safe, accurate and reliable testing of low voltage technologies
  • Improved vectorless test technologies
    • For reliable testing of microBGA and small package components and connectors
    • New techniques for combining BSCAN and Framescan technologies
  • Reduced access test solutions
    • For gaining test access to nets that do not have physical test access
  • Flexible boundary scan solutions
    • Allows 3rd Party boundary scan tests to be re-used
    • Teradyne Native 1149.1 boundary scan support
  • Graphical mouse-based debug and production user interfaces
    • Software that is easier to use and learn
  • Configurable for high volume requirements
    • Optimized test throughput tools
    • Integrated inline solutions
    • Concurrent test capabilities