Download
1 / 26
260 likes | 347 Views
This study delves into the critical metric of end-to-end packet delay by analyzing delays incurred at single routers. It provides a comprehensive overview of router monitoring, delay analysis, and modeling, bridging performance metrics with queuing theory. By understanding the nuances of store-and-forward datapaths, packet reconstruction, and output link scheduling, the study sheds light on transit time variations and FIFO queue dynamics. The research also emphasizes the importance of modeling fluid queues with delay elements and validates the model's accuracy in evaluating router performance under different arrival patterns. With a focus on busy periods and congestion levels, the study presents empirical findings and future research directions to enhance the reporting scheme and align practical performance with theoretical frameworks.
E N D
Bridging Router Performance and Queuing Theory N. Hohn*, D. Veitch*, K. Papagiannaki, C. Diot *: University of Melbourne
Motivation • End-to-end packet delay is an important metric for performance and SLAs • Building block of end-to-end delay is through router delay • We measure the delays incurred by all packets crossing a single router
Overview • Full Router Monitoring • Delay Analysis and Modeling • Delay Performance: Understanding and Reporting
Overview • Full Router Monitoring • Delay Analysis and Modeling • Delay Performance: Understanding and Reporting
Not part of the system Store & Forward Datapath • Store: storage in input linecard’s memory • Forwarding decision • Storage in dedicated Virtual Output Queue (VOQ) • Decomposition into fixed-size cells • Transmission through switch fabric cell by cell • Packet reconstruction • Forward: Output link scheduler
Not part of the system Δ Store & Forward Datapath • Store: storage in input linecard’s memory • Forwarding decision • Storage in dedicated Virtual Output Queue (VOQ) • Decomposition into fixed-size cells • Transmission through switch fabric cell by cell • Packet reconstruction • Forward: Output link scheduler
Minimum Transit Time Packet size dependent minimum delay Δ(L), specific to router architecture and linecard technology
Not part of the system Δ(L) FIFO queue Store & Forward Datapath • Store: storage in input linecard’s memory • Forwarding decision • Storage in dedicated Virtual Output Queue (VOQ) • Decomposition into fixed-size cells • Transmission through switch fabric cell by cell • Packet reconstruction • Forward: Output link scheduler
Modeling Fluid queue with a delay element at the front
Modeling results • Our crude model performs well • Use effective link bandwidth (account for encapsulation) • Small gap between router performance and queueing theory! • The model defines Busy Periods: time between the arrival of a packet to theempty system and the time when the system becomes empty again.
Overview • Full Router Monitoring • Delay Analysis and Modeling • Delay Performance: Understanding and Reporting
On the Delay Performance • Model allows for router performance evaluation when arrival patterns are known • Goal: metrics that • Capture operational-router performance • Can answer performance questions directly • Busy Period structures contain alldelay information
A ts D Busy periods metrics
Issues • Report (A,D) measurements • There are millions of busy periods even on a lightly utilized router • Interesting episodes are rare and last for a very small amount of time
Conclusion • Results • Full router empirical study • Delay modeling • Reporting performance metrics • Future work • Fine tune reporting scheme • Empirical evidence of large deviations theory
