CSCE 211: Digital Logic Design

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CSCE 211: Digital Logic Design. Chin-Tser Huang [email protected] University of South Carolina. Chapter 7: The Design of Sequential Systems. Review: Design Process for Combinational Systems. Step 1: Represent each of the inputs and output in binary.

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### CSCE 211:Digital Logic Design

Chin-Tser Huang

[email protected]

University of South Carolina

### Chapter 7: The Design of Sequential Systems

Review: Design Process for Combinational Systems

Step 1: Represent each of the inputs and output in binary.

Step 1.5: If necessary, break the problem into smaller subproblems.

Step 2: Formalize the design specification either in the form of a truth table or of an algebraic expression.

Step 3: Simplify the description.

Step 4: Implement the system with the available components, subject to the design objectives and constraints.

Design Process for Sequential Systems

Step 1: From a word description, determine what needs to be stored in memory, that is, what are the possible states.

Step 2: If necessary, code the inputs and outputs in binary.

Step 3: Derive a state table or state diagram to describe the behavior of the system.

Step 4: Choose a state assignment, that is, code the states in binary.

Step 5: Choose a flip flop type and derive the flip flop input maps or tables.

Step 6: Produce the logic equation and draw a block diagram (as in the case of combinational systems).

Revisit Continuing Example 6

CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times.

State Assignment of CE 6

We use assignment (a) in our discussion of CE6.

K-map for Next State

q1* = x q2 + x q1

q2* = x q2´ + x q1

Design with D Flip Flops

Therefore,

D1 = x q2 + x q1

D2 = x q´2 + x q1

Design with JK Flip Flops

J1 = xq2 K1 = x´z =q1q2

J2 = x K2 = x´ + q´1

Design with T Flip Flops

T1 = x´q1 + xq´1q2 z =q1q2

T2 = x´q2 + xq´2 + xq´1q2

Synchronous Counter
• A synchronous counter is a device with no data input that goes through a fixed sequence of states on successive clocks
• The output is often just the state of the system, i.e., the contents of all of the flip flops
• So no output column is required in the state table
Another Example: Up/Down Counter
• A counter that can count up or down according to a control input
• Counts up when x=0
• Counts down when x=1
Design with JK Flip Flops

JA =KA = 1

JB =KB =x´A +xA´

JC =KC =x´BA +xB´A´

Another Example: Decimal Counter
• A decimal counter goes through the sequence

0 1 2 3 4 5 6 7 8 9 0 1 …

• Can you develop the truth table and then K-maps for the next state of each bit?