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Upgrade Cal. Trigger R&D

Upgrade Cal. Trigger R&D. M. Bachtis , A. Belknap, M. Cepeda , S . Dasu, E. Friis , R . Fobes , T. Gorski , M . Grothe , P. Klabbers, I. Ojalvo , I . Ross, W.H. Smith Physics Department K . Compton, A. Farmahini-Farahani , T . Gregerson , M . Schulte, D. Seemuth ECE Department

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Upgrade Cal. Trigger R&D

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  1. Upgrade Cal. Trigger R&D M. Bachtis, A. Belknap, M. Cepeda, S. Dasu, E. Friis, R. Fobes, T. Gorski, M. Grothe, P. Klabbers, I. Ojalvo,I. Ross, W.H. Smith Physics Department K. Compton, A. Farmahini-Farahani, T. Gregerson,M. Schulte, D. Seemuth ECE Department U. Wisconsin – Madison Upgrade Trigger Meeting November 8, 2011

  2. BU/UW AMC13 MMC Integration • AMC13 MMC: • Collaboration between Wisconsin and Boston University • Wisconsin reference circuit on AMC13 Tongue 2 board • Wisconsin design for MMC software • Version 1.2 Supports: • Monitoring of available voltage & temperature sensors on T2 (+12V, +3.3V, ambient temperature) • Arbitration with Crate MCH for delivery of payload +12V power • Successfully tested with both NAT and Vadatech MCHs • Remote transfers from Linux PC to T2 Spartan 6 via custom IPMI commands and MMC SPI interface

  3. BU/UW AMC13 MMC Integration Wisconsin MMC on Boston University AMC13 Spartan-6 (TTC Processor ) on Tongue 2 Virtex-6 (DAQ Processor ) on Tongue 1

  4. BU/UW AMC13 MMC Integration MMC console (COM port) Vadatech UTC002 MCH (courtesy of Vadatech Corp.) MMC Console Output @ startup with NAT-MCH NAT MCH (need FW Version 2.10 for AMC13 support)

  5. UW MMC Code • Version 1.2 downloadable at www.hep.wisc.edu/ecad/SLHC/MMC/AMC13_MMC_v1p2_download • AVR Studio 5 Project • IPMI Custom Command Spec • Sample Linux custom command programs using ipmitool interface to NAT MCH • Still to do: • Evaluate ipmitool interface to Vadatech • Auto-detection of Spartan-6 SPI configuration interface (v 1.3) Special adapter cable for programming (UW lab) JTAGIC3 Programmer (~$200 USD)

  6. Microblaze Processor Demonstrator on AMC13 V6 • Includes Microblaze, MPMC and GbE cores + clock, UART, etc. • Usage for XC6VLX130T: • Slice Regs: 6% • Slice LUTs: 11% • Block RAM: 30% (includes 128 KB as processor store) • Next Steps: • GbE and TCP/IP implementation (lwIP) • IPbusServer (UDP/TCP) Mod to add 2nd USB FT232R COM interface (S6 pass-through) for V6 Microblaze Console Console I/O for DDR3 Memory Test

  7. UW Calorimeter Trigger Processor (CTP) Prototype Backplane Side Front Panel Side Secondary Power Supplies LHC Clock Link Clock Conditioning Circuitry SDRAM 12-Channel Optical Receiver Up to 6.4 Gbps TTC/DAQ to AMC13 GbE 12-Channel Optical Receiver Up to 6.4 Gbps 12x8 Region Processing FPGA XC6VHX250T (-2 GTX links) Front End FPGA XC6VHX250T (-2 GTX links) Ports 4-7 (MCH1) 12-Channel Optical Receiver Up to 6.4 Gbps Ports 8-11 (MCH2) Ports 12-15 (BP fabric) 12-Channel Optical Receiver Up to 9.6 Gbps Ports 17-20 (BP fabric) 16 bidir. BP ports @ Up to 6.4 Gbps 12-Channel Optical Transmitter Output 2:1 Mux Up to 6.4 Gbps MMC FPGA Image Flash (Parallel) IPMI 48 inputs × 12 outputs @ 6.4 Gbps

  8. UW CTP CAD Screen Shot • Current Status: Updating connections to get favorable routes • Mostly capacitors and power supplies! • Have 16 XC6VHX250T FPGAs from Xilinx donation • First boards at end of Q1 2012 12V Power Supplies MMC Front EndFPGA 48X TP RX Links Reg. Proc. FPGA 12X Tx Links

  9. Custom Backplane Fabric (VT892 Style Crate) Concept: Define a passive fabric for the otherwise unused ports 12-15 and 17-20 of AMC slots 2-11 to support the Compact Calorimeter Trigger & other architectures Point-to Point Backplane Connection Legend: η = -5.00 η = +5.00 η = 0 η = 0 2 4 6 8 10 14-15 14-15 14-15 14-15 14-15 12-13 19-20 17-18 17-18 η 19-20 CTP CTP CTP CTP CIO-U 12-13 24 towers in φ 3 5 7 CIO-L 9 11 Φ Intra-Crate 14-15 17-18 14-15 12-13 19-20 CTP CTP CTP CTP 12-13 12-13 12-13 12-13 Φ On/off Crate Paths Compact Trigger Use Example Px Py

  10. MicroTCA Backplane Custom Fabric Block Diagram 12 20 6 13 19 14 18 15 14 17 15 14 15 14 15 15 14 17 10 2 17 19 4 17 19 8 17 19 18 18 20 18 20 18 20 18 17 17 18 12 1 13 12 13 13 13 12 12 12 15 14 15 15 15 14 14 14 11 3 17 19 5 17 19 9 17 19 19 20 19 17 20 19 18 20 18 20 18 20 18 20 13 12 12 13 12 13 12 13 15 17 14 7 18 19 12 20 13

  11. Compact Trigger Hardware Crosspoint I/O (CIO) Backplane Side Front Panel Side QSFP+ 4 ch Transceiver Ports 4-7 Tx (MCH1) Up to 6.4 Gbps 2:1 Mux Ports 4-8 Rx (MCH1) QSFP+ 4 ch Transceiver Ports 8-11 Tx (MCH2) Up to 6.4 Gbps 2:1 Mux Ports 8-11 Rx (MCH2) 16 bidir. BP ports @ Up to 6.4 Gbps Fan-out QSFP+ 4 ch Transceiver Ports 12-15 Rx Up to 6.4 Gbps Ports 12-15 Tx QSFP+ 4 ch Transceiver Up to 6.4 Gbps Ports 17-20 (BP fabric) MMC Secondary Power Supplies 16× Bidirectional @ Up To 6.4 Gbps IPMI

  12. MicroTCA Backplane • Custom Passive Fabric • 88 differential pairs added to unconnected ports of VT892-type backplane • Slots 2-5, 8-11 have geographically consistent port assignments • 12-15 are “left/right”, 2 connections per direction • 17-20 are “up/down”, 2 connections per direction • Slots 1/12 6-7 are hubs for inter-crate connections and have horizonal or vertical port symmetry • Crates can be chained left/right or up/down with optical connections (e.g., CIO card) • All slots also have dual star connections to MCH slots on ports 4-7 (MCH1) and 8-11 (MCH2) • Slots allocated to minimize physical distances between endpoints • Plan: Commission Vadatech to add fabric to VT892-type backplane • Issue PO in 2011 • Estimate delivery in Q2 of 2012 • Vadatech will issue new part number, backplane will be compatible with existing VT892 applications

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