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Chapter 5 Internal Memory Technology ( Cont. )

Lecture 2. Chapter 5 Internal Memory Technology ( Cont. ). Refreshing. Refresh circuit included on chip. Disable chip. Count through rows. Data is read out and written back into the same location  each cell is refreshed. Takes time. Slows down apparent performance. Chip Packaging.

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Chapter 5 Internal Memory Technology ( Cont. )

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  1. Lecture 2 Chapter 5 Internal Memory Technology (Cont.)

  2. Refreshing • Refresh circuit included on chip. • Disable chip. • Count through rows. • Data is read out and written back into the same location  each cell is refreshed. • Takes time. • Slows down apparent performance.

  3. Chip Packaging • 16-Mbit DRAM, 4M x 4. • Updatable  data pins in/out. • WE: Write Enable • OE: Output Enable • NC: No Connect  even # of pins • 8-Mbit EPROM chip, 1M x 8. • One-word-per-chip package. • Address: A0-A19, Data: D0-D7 • Vcc; power, Vss: ground, CE: chip enable, Vpp: programming voltage.

  4. Module Organization • Available: 256 k x 1-bit chips 256 k byte memory

  5. Module Organization (2) • Available: 256 k x 1-bit chips 1 M byte memory

  6. Error Correction • Semiconductor memory is subject to errors. • Hard Failure • Permanent physical defect. • Memory cells cannot store data: stuck at 0 or 1, or switching. • Caused by harsh environments, manufacturing defects, or wear. • Soft Error • Random, non-destructive event that alters contents of one or more memory cells. • No permanent damage to memory. • Caused by power supply problems or alpha particles. • Detected/corrected using Hamming error correcting code.

  7. Error-Correcting Code Function

  8. Hamming Error-Correcting Code Data bits: 1110 B A 1 0 1 1 0 0 1 Discrepancies 0 C Parity bits Chosen so that total number of 1s in each circle is even. By checking the parity bits, discrepancies are found  error can be easily found and corrected.

  9. Error-Correcting Codes • A word consists of M data bits and K check (redundant) bits. • N = M + K • Codeword: data bits + check bits. • Hamming distance: # of bit positions in which two codewords differ. • 11001001, 10100001  Hamming distance = 3  3 bit errors are needed to convert one into the other. • In a code, not all 2N codewords are legal. • Hamming distance of the whole code: min. Hamming distance between 2 legal codewords. • To detectd errors, distance d+1 code is needed. • To correctd errors, distance 2d+1 code is needed.

  10. Error Detection/Correction • Detection: parity bit. • Distance = 2  can detect up to 1 bit error. • e.g., 101101010110100 • Correction: Consider a code with 4 valid codewords: 0000000000, 0000011111, 1111100000, 1111111111 • Distance = 5  can correct up to 2 bit errors. • If 0000000111 arrives,  0000011111 • If 0000000000 becomes 0000000111 due to 3 errors  cannot be corrected properly.

  11. Single Bit Error Correction Design a code to correct all single bit errors. • M = data bits, K = check bits • N = M + K • M + K + 1 ≤ 2K • Each of the 2M legal words has N illegal codewords at distance 1. • Thus, each of the 2M legal words requires (N + 1) bit patterns dedicated to it. • (N + 1) 2M ≤ 2N M + K + 1 ≤ 2K

  12. Hamming Code • Check (parity) bits are used to identify a single bit error. M + K + 1 ≤ 2K => 9 + K ≤ 2K K = 4 1 0 0 1 1 0 1 0 Data bits 5 3 6 11 4 9 12 1 10 2 7 8 0 0 ? ? 1 1 ? 0 0 1 ? 1 0 1 0 1 Codeword 1 Bit position 1: 0 0 1 Bit position 2: 1 0 1 Bit position 1 ? 1 ? Bit position 2 1 0 1 1

  13. Hamming Code (2) • Assume error in bit 9 • Recompute the check bits at the receiver. • Bit 1 = 1 (error) • Bit 2 = 1 • Bit 4 = 1 • Bit 8 = 1 (error) • Error is in bit position = 1 + 8 = 9  flip it (correction). 5 3 6 11 4 9 12 1 10 2 7 8 0 0 1 1 1 0 0 1 0 1 0 1 0 Codeword

  14. Reading Material • Stallings, chapter 5, pages 166 – 173

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