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Some Issues in System-Level Power Optimization Abdil Rashid Mohamed, ESLAB, Ph.D. student PowerPoint Presentation
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Some Issues in System-Level Power Optimization Abdil Rashid Mohamed, ESLAB, Ph.D. student. Presentation Organization. 10 15 - 11 15  Abdil System-level Power/Energy Optimization Techniques 11 15 - 11 30  coffee break 11 30 - 12 00  Mehdi part I 13 15 -13 45  Mehdi part II

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Some Issues in System-Level Power Optimization

Abdil Rashid Mohamed, ESLAB, Ph.D. student

presentation organization
Presentation Organization
  • 1015 - 1115  Abdil
    • System-level Power/Energy Optimization Techniques
  • 1115 - 1130  coffee break
  • 1130 - 1200 Mehdi part I
  • 1315 -1345 Mehdi part II
    • Dynamic Power Management
    • Low Power Software Generation
  • 1345 – 1400 coffee break
  • 1400 – 1500 Aleksandra
    • Low Power/Energy Scheduling for Real–time Systems
  • Motivation - the compeling need for low power systems
  • Power reduction at
    • conceptualization and modeling levels
    • design level - design of power efficient
      • hardware units
      • memories and
      • communication buses
  • Conclusion
why low power electronic systems
Why Low Power Electronic Systems ?
  • Power/Energy is expensive, non-renewable and negatively impacts on environments
  • Extend life of battery powered systems: laptops, PDAs.
  • In desktops and servers high power consumption raises temperature and deteriorates performance and reliability.
  • Increases need for cooling mechanisms.
  • Technical feasibility of high performance computation due to heat extraction
  • Power efficiency has: economic, ecological and ethical reasons.
  • It worth mention: power crisis in California, Tanzania.
power reduction techniques
Power Reduction Techniques
  • Static techniques for low power
    • Applied at conceptualization and design time
    • Synthesis for low power
    • Compilation for low power
  • Dynamic techniques for low power
    • Dynamic power management (DPM) - use run time behavior to reduce power consumption when system is serving light load or when idle
      • Dynamic voltage scaling (DVS)- change voltage at run time to manage power
      • Shutdown unused I/O devices, NIC, display or HDs
hardware technologies for low power
Hardware Technologies for Low Power
  • Very low supply voltage technologies.
  • Multiple supply voltages on a single chip.
  • Techniques for handling dynamically variable supply voltage and/or clock speed.
system organization and sources of power consumption
System Organization and Sources of power Consumption
  • Main consumers of energy in HW are:
    • computation, communication and storage units.
  • Does software consume power ?
  • Energy efficient design of HW/SW systems:
    • Need support of a design flow that takes power consumption into account at all steps of the design process.
    • Power estimation metrics at different abstraction levels
    • Drawbacks: Metrics are less accurrate at higher levels
    • Power depends on implementation specific details
power consideration at all levels and dimensions
Power Consideration at All Levels and Dimensions

Organized in two dimensional taxonomy

Computation -> communication -> storage




conceptualization and modeling specification and implementation models

Classes of Systems

General-purpose Systems

Special-purpose Systems

System modeling Styles

Implementation models

Functional models

Executable Non-executable

Conceptualization and Modeling:Specification and Implementation Models

Which modeling style is good for power consideration ?

specification and implementation models
Specification and Implementation Models
  • Functional models
    • addresses functionality and requirements
    • executable (VHDL, C++, Java; for simulation ) or non executable ( task graph )
  • Implementation models
    • describe the target realization for systems.
    • system complexity: modular, component oriented, hierarchical.
    • Implementation models for energy efficient systems modelling:
      • Spreadsheet model-expresses a combination of components and evaluates overall energy budget
      • Power state machine model captures the power consumption of systems and their constituents as they evolve through a sequence of operational states.
energy efficient design from executable functional models
Energy Efficient Design from Executable Functional Models
  • Algorithm selection for low power
    • For a given common function, make a library of multiple different algorithms
    • Characterize each algorithm with performance & power
    • Perform system optimization by:
      • heuristic to select an implementation algorithm and supply voltage that trades off performance for power.
  • Algorithm computational energy
    • Computational energy of the algorithm can be estimated using CDFG
    • Characterize each elementary operation with a computational energy metric
    • Compose rules to compute energy cost of a complex CDFG.
    • Energy of elementary operations is obtained by assuming implementation style and extract cost per operation through experiments
energy efficient design from executable functional models1
Energy Efficient Design from Executable Functional Models
  • Algorithm communication and storage energy
    • communication and storage cost is hidden in specifications
    • storage and communication energy: relate to locality of computation data
    • data variables with long life time -> increased storage need -> more power
    • problem: locality analysis from CDFG is hard, information not explicitly available
  • Computational kernels
    • is an inner loop of an algorithm where most of the time is spent during execution
    • extract them by profiling data on executable system level model
    • implement on dedicated power-optimal hardware
    • during execution of kernel, rest of system can be shutdown, hence save power
power estimation for non executable functional models task graph

Link Pow Speed

L1 10*BW 40*BW

L2 20’BW 30*BW

Mem Pow Speed

M1 50*S 12*S

M2 60*S 15*S

Power PE1 PE2

T1 10 20

T2 15 30

T3 10 20

T4 11 7

T5 32 41

T6 7 10

T7 12 22

Time PE1 PE2

T1 5 8

T2 7 12

T3 4 7

T4 8 5

T5 20 35

T6 2 3

T7 11 17










Period < 100


Deadline = 70












Power Estimation for non executable functional models: Task Graph

PE allocation, binding, scheduling

PE1: {T1->T2->T3->T7->T4}

PE2: {T5->T6}


PE1 <->PE2: L1

Mem allocation

M1: {T5, T6}

M2: {T1, T2, T3, T4, T7}

task graph contd
Task Graph (contd. )
  • Computation energy:

EPE = EPE1 + EPE2 = (10+15+10+11+12) +(41+10) = 109

  • Storage energy:

EM = EM1 + EM2 = (0.5+0.3).50 +(0.1+0.1+0.3+0.1+0.1).60 = 88

  • Communication energy:

ECom = EPE1->PE2 + EPE2->PE1 = (0.1+0.4).20 = 10

  • Total energy:

E = EPE+EM+Ecom = 109+88+10 = 206

  • Heuristic to minimize power for the task graph implementation
  • Drawbacks: Need for exhaustive pre-characterization and loss of accuracy due to lack of information on the effects caused by hardware sharing.
energy efficient design from implementation models
Energy efficient design from implementation models
  • Spreadsheet model
    • Expresses a combination of components and evaluates overall energy cost
    • Useful when designing systems that use specific parts and interconnect topologies
    • Estimates the impact of a component on the power budget
    • Total power is the sum of the power of all components.
    • Power consumption of all components is taken from data sheets and collected in a spreadsheet.
    • Drawback: do not model interaction between components
energy efficient design from implementation models1

P=250mW, activity




P=40 μW





P=0 μW


PSM for a memory component

Energy efficient design from implementation models
  • Power State Machine (PSM)
    • State based model for system components
      • states represent modes of operations
      • arcs represent legal transitions between op. modes
      • states are labelled with power dissipation values
      • transitions are labelled with triggering events, energy costs and transition times.
    • Advantages:
      • study how system reacts to different workloads
      • model interactions between components
      • analyze the effects of power management.
    • Drawbacks: complex component model
low power application specific units
Low Power Application Specific Units
  • Usually gives better power efficiency, but have low flexibility
  • Power reduction techniques: low power RTL, logic level and physical level techniques
    • Power Driven Voltage Scaling (PDVS) and scaling down Vdd, reduce power, but performance may diminish.
    • multiple supply voltages on a single chip (globally asynchronous and locally synchronous systems (GALS))
    • reduce clock frequency, load capacitance and switching activity.
    • set clock frequency of a component that is not performing useful work to zero and nullify dynamic power consumption of that component
  • A. Hemani: transformed single clock industrial designs into GALS - 70% power reduction
low power through switching activity reduction
















+1 and +3 bound to the same adder







Power efficient schedule & binding

Less power efficient schedule and binding

Low Power through Switching Activity Reduction
  • Reduce the number of basic operations, -> transform DFG to minimize the number of operations
  • Reduce switching of the inputs to functional unit (FU) -> increase correlation between successive patterns at the input of FU.
  • Scheduling and binding for reduced switching activity
application specific processors
Application Specific Processors
  • Provides high degree of flexibility, programmability, and reuse
  • Not energy efficient and have several disadvantages:
    • Power overhead for instruction fetch and decoding
      • not an issue for computation units with hardwired control
    • Perform computation as a sequence of instruction execution ->power overhead
      • can not take full advantage of algorithmic parallelism.
    • Can perform a limited number of elementary operations specified by ISA
  • Low power technique: Instruction subsetting -> reducing the number of instructions supported by ASIP
    • Reduce instruction decoding and micro architectural complexity
core processors
Core Processors
  • Reduce power by:
    • Voltage scaling
      • low power version of μPs has low supply voltage
    • Dynamic variable voltage supply
    • Low power micro architecture design (critical path redesign)
      • avoid useless switching activity in idle units
    • Special instructions - enhance power & performance
      • subword parallel, special addressing mode, multiply-accumulate
      • problem: hard to design compilers for special instructions
design of power efficient memory subsystems
Design of Power-Efficient Memory Subsystems
  • Memory accesses are slow and consume more power with increasing memory size
    • reduce memory storage requirements of the applications
    • during system conceptualization use principle of temporal locality to reduce memory storage requirement
    • improve locality and reduce need for temporary storage of results of computation by consuming them ASAP
    • Reduce memory need by data compression
  • Advanced hierarchical memory architectures for low power
hierarchical memory models

Level 3

Level 2

Level 1

Level 0







Hierarchical Memory Models
  • Power and access time increases as we move up memory hierarchy
  • Exploit non uniformities in access frequencies of data
    • Place frequently accessed locations in low hierarchies to minimize average cost per access
low power communication resources
Low Power Communication Resources
  • At physical level communication power is reduced :
    • scaling down the voltage swing on the high capacitance wires of the bus
    • scaling down the average number of signal transitions
  • low power data encoding
  • Arbitration protocols
    • bus access control
    • reduce bus power by scheduling & binding highly correlated data streams consecutively on the bus
low power bus design
Low Power Bus Design
  • Low power bus design techniques
    • lower switching activity, reduce capacitance to be switched
    • minimize bus length by module placement and bus routing
    • build hierarchical bus
  • Bus segmentation –
    • transform a long heavily loaded global bus into a partitioned multistage network by inserting pass transistors on the bus lines to separate various local buses (segments)
    • partitioning can reduce bus power by 60%
  • A balance between power and performance
  • Designing energy efficient systems is a multifaceted problem: high degree of freedom for power reduction at all abstraction levels
  • Main referenece: Benini, D. Micheli, ”System level Power Optimization: Techniques and Tools”


power crisis
Power Crisis
  • It worth mention: Power crisis in California, Tanzania.
  • Companies install their own power plants to cope with the problem.
  • 12$ additional surcharge per day per room due to increased power cost at some hotels.
  • Refereences from:
  •,show/id,6362/sid,14 Keeping the Silicon Burning: California's Power Crisis Concern for Data Centers The lights in California may fade, but data and Web pages are still served up. “What we’ve done is protect our customers,” asserts Lloyd Howison, senior manager of construction and engineering for Web hosting at WorldCom. Data centers themselves contribute significantly to the power problem. Full of servers, disk drives, networking gear and cooled air, data centers consume a staggering amount of electricity. Reportedly, a data center gobbles as much power as six office buildings. A widely publicized 1999 study estimated that eight percent of the U.S. consumption of electricity was Internet related.
  • An Internet service provider data warehouse with 8,000 servers consume as much as 2 MW of power. A household in Tanzania gets only about 600KWh per month.
  • NB: “Since embedded systems are increasingly being used and are massively produced not only for mobile devices, but most of them end up in stationary home based or industry based devices, every Mw of power that can be saved will result in tremendous power savings in total due to mass production of similar embedded VLSI systems” by Abdil.
  • Since energy consumption of electronic systems will scale up as they become more complex and integrated, energy-efficient electronic system development is mandated by economic, ecological and ethical reasons.

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