Computer Architecture Guidance. Keio University AMANO, Hideharu hunga@am ． ics ． keio ． ac ． jp. Contents. Techniques of two key architectures for future system LSIs Parallel Architectures Reconfigurable Architectures Advanced uni-processor architecture
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Techniques of two key architectures for future system LSIs
→Special Course of Microprocessors (by Prof. Yamasaki, Fall term)
A parallel architecture consists of multiple processing units
which work simultaneously.
Hennessy & Petterson’s
Computer Architecture: A quantitative approach
Tightly CouplingIncreasing of simultaneous issued instructions vs. Tightly coupling
Multiple instructions issue
Multiple Threads execution
On chip implementation
Shared memory, Shared register
Connecting Multiple Processors
Parallel Architecture: Performance Centric!
1bit serial ALU
provides shared memory which can be accessed from all processors with the same manner.
provides shared memory but not uniformly accessed.
provides no shared memory. Communication is done with message passing.
Single chip multiprocessorUMA
The gap between switch and bus becomes small
Logical address space
MainMemory is connected directly with HubChip
1 cluster consists of ２PE.
Bus connected UMA
Switch connected UMA
Data flow architecture
Demand driven architecture
Data streams are inserted into an array of special purpose computing node in a certain rhythm.
Introduced in Reconfigurable Architectures
A process is driven by the data
Also introduced in Reconfigurable Systems