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ITRS Perspective on the Compact Model Developments

ITRS Perspective on the Compact Model Developments. Herve Jaouen 1 , Bert Huizing 2 , Jürgen Lorenz 3 , Wladek Grabinski 4 (presenter) 1 STMicroelectronics, Crolles, France 2 NXP, Eindhoven, The Netherlands 3 Fraunhofer IISB, Erlangen, Germany 4 GMC, Commugny, Suisse. OUTLINE:.

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ITRS Perspective on the Compact Model Developments

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  1. ITRS Perspective on the Compact Model Developments Herve Jaouen1, Bert Huizing2, Jürgen Lorenz3 , Wladek Grabinski4 (presenter) 1STMicroelectronics, Crolles, France 2NXP, Eindhoven, The Netherlands 3Fraunhofer IISB, Erlangen, Germany 4GMC, Commugny, Suisse

  2. OUTLINE: • ITRS Overview • Objective of the ITRS • Organization of the ITRS • TCAD Challenges • Short Term (until 2019) • Long-Term (until 2026) • ITRS for Compact Modeling

  3. About the ITRS • The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The sponsoring organizations are: • European Semiconductor Industry Association (ESIA) • Japan Electronics and Information Technology Industries Association (JEITA) • Korean Semiconductor Industry Association (KSIA) • Taiwan Semiconductor Industry Association (TSIA) • United States Semiconductor Industry Association (SIA)

  4. The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the products that employ such devices, thereby continuing the health and success of the semiconductor industry Set benchmark/guidelines for R&D: SRA, Work Programs of subsidy frameworks US event originally (NTRS), since 1998 world wide effort Sponsored by 5 Semiconductor Industry Associations (Korea, Taiwan, Japan, Europe, US) Pre-competitive; 15 year scope Output: biyearly update text; yearly update tables Participants: Manufacturers, Suppliers, Academia, Consortia, Gov Labs

  5. Organization of the ITRS International Roadmap Committee (Executive Committee) Public Voice of the ITRS Representatives from 5 regional SIA’s (US, Europe, Japan, Korea, Taiwan) Provides direction: content, scope, timing, etc TWGs (Technology Working Groups) 16 (->17) teams of experts in major technology disciplines 3 live meetings a year: US, Asia, Europe

  6. TWGs (Technology Working Groups) The working groups, known as TWGs, focus on technologies that are crucial to the design, materials, and manufacture of semiconductors, as well as the factory sciences, process control, metrology, and environmental aspects. The working group members include subject matter experts that represent all sectors of the industry-chip manufacturers, equipment suppliers, and R&D experts. System Drivers Design Test & Test Equipment Process Integration, Devices, & Structures RF & A/MS Technologies Emerging Research Devices Emerging Research Materials Front End Processes Lithography Interconnect Factory Integration Assembly & Packaging Environment, Safety, & Health Yield Enhancement Metrology Modeling & Simulation MEMS

  7. Technology Modeling and Simulation • Technology Modeling and Simulation covers the region of the semiconductor modeling world called extended TCAD, and it is one of the few enabling methodologies that can reduce development cycle times and costs. Extended TCAD, within the scope of this document, covers the following topical areas: • Front end process modeling, simulation of the physical effects of manufacturing steps used to build transistors up to metallization, but excluding lithography • Lithography modeling-modeling of the imaging of the mask by the lithography equipment, the photoresist characteristics and processing • Device modeling-hierarchy of physically based models for the operational description of active devices • Interconnect and integrated passives modeling-the operational response (mechanical, electromagnetic, and thermal properties) of back-end architectures; • Circuit element modeling-compact models for active, passive, and parasitic circuit components, and new circuit elements based on new device structures; • Package simulation-electrical, mechanical, and thermal modeling of chip packages • Materials modeling-simulation tools that predict the physical properties of materials and, in some cases, the subsequent electrical properties • Equipment/feature scale modeling-hierarchy of models that allows the simulation of the local influence of the equipment (except lithography) on each point of the wafer, starting from the equipment geometry and settings • TCAD for design, manufacturing and yield-the development of additional models and software to enable the use of TCAD to study the impact of inevitable process variations and dopant fluctuations on IC performance and in turn design parameters, manufacturability and the percentage of ICs that are within specifications • Numerical methods-all algorithms needed to implement the models developed in any of the other sections, including grid generators, surface-advancement techniques, (parallel) solvers for systems of (partial) differential equations, and optimization routines

  8. ITRS Overview • International Technology Roadmap for Semiconductors ITRS • Modeling and Simulation Chapter • Also relevant: Modeling section of „Emerging Research Materials“ Chapter

  9. Overview of ITRS Process Manufacturers, Suppliers, Academia, Consortia, Government Labs Determine Roadmap Objective Steering CommitteeIdentifies TechnologyDrivers TWGsIdentifies/ UpdatesKeyChallenges CommunityInputs to Contributors TWGsQuantify Technology Requirements CommunityImplementsRoadmap Revises & Distributes to Industry Community TWGsIdentify Innovation Areas Reach Consensus (peer review) ITRS: International Technology Roadmap for Semiconductors TWG: Technology Working Group

  10. ITRS Process Essentials • Some essentials on ITRS process • Industrial perspective: ITRS governed by semiconductor industry; contributions from suppliers and research • Top-level specifications by IRC and ORTC – e.g. on scaling speed • 17 ITWGs derive challenges and requirements for focus and cross-cut areas – Modeling and Simulation on crosscut ITWG • New roadmap each odd year – even years only update of tables • Limited publication in July, full publication in December (Winter meeting and internet) • Modeling and Simulation ITWG • Currently 35 members – 17 industry, 8 suppliers, 10 research • Discussion starts from analysis of requirements of other ITWGs w.r.t M&S  cross-cut texts • Challenges, requiremens and chapter texts derived • State-of-the-art vs. requirements labelled in colour codes

  11. ITRS Documentation Output Outline ITRS Executive Summary Overall Roadmap Technology Characteristics 16 Chapters (from 2011: 17) Each Chapter also contains tables Difficult challenges Near term and long term requirements Accuracy tables for most relevenant FOMs Color coding system to indicate issues

  12. TCAD Challenges • Lithography simulation including EUV • EMF simulation • Resist simulation • Double patterning, EUV, ebeam, Direct Self-Assembly • Metrology/Characterization • OPC and defects • ITRS Short Term • (until 2019) • Front-end processmodelingfornanometerstructures • Implantation; diffusion/(de-)activation, segregation; epitaxy • New materialsandprocesses • Defects, damage, stress • 3D meshing 2011 ITRS draft, Jul/Aug 2011

  13. TCAD Challenges • Integrated modelingofequipment, materials, featurescaleprocessesandinfluences on deviceandcircuitperformanceandreliability, includingrandomandsystematicvariability • Deposition, etching, CMP, ECP, waferpolishing/thinning ITRS Short Term (until 2019) • Nanoscaledevicesimulationcapability: Methods, modelsandalgorithms • Models andsoftware • Noveldevicearchitectures, channelandgatestackmaterials • Fluctuations/variations; reliability • Efficientand robust QM-basedsimulation 2011 ITRS draft, Jul/Aug 2011

  14. TCAD Challenges • Electro-thermal-mechanicalmodelingforinterconnectsandpackaging • Co-simulation electro-thermal-mechanical • Feature scaleto 3D ICs andpackages • Novelmaterials • Interfaces andthinlayers • Variability, reliability ITRS Short Term (until 2019) • Circuit elementandsystemmodelingfor high frequency (upto 300 GHz) applications • Fromdevice/interconnectto dies andpackages • Noveldevicearchitectures • More-than-Moore • Noise, variations, aging, reliability 2011 ITRS draft, Jul/Aug 2011

  15. TCAD Challenges ITRS Long-Term (until 2026) Modeling of chemical, thermomechanical and electrical properties of new materials Nano-scale modeling for Emerging Research Devices and interconnects including Emerging Research Materials Optoelectronics modeling NGL simulation 2011 ITRS draft, Jul/Aug 2011

  16. ITRS for Compact Modeling Historically analog simulation drove development of circuit element models. Today and for future needs faster models and improved convergence required Device models will include many more detailed effects • Parasitic effects, like series resistance, inductance and capacitance • Quantum effects • Leakage (gate, junction, off-state) • Noise, distortion and non-quasi-static effects • Variability at local level or at global level resulting from layout configuration and process variability

  17. ITRS for Compact Modeling • Compact models for future CMOS generations should model new effects correct, i.e. • mobility-enhanced channels and high-k gate leakage • fully depleted channels, like FD SOI-CMOS, FinFET, multy gate FET • non-classical, new architecture CMOS devices • ultra short channels (L <10nm) • ballistic effects • quantum mechanical interactions • RF models extend to the 100 GHz range • process compact models (PCM) based on pre-calibrated TCAD simulations • local process variability and statistics via SPICE parameters

  18. Non-CMOS Compact Modeling • For non-CMOS devices the number of options in ITRS chapters is still very large, requiring huge efforts in the modeling domain • For bipolar devices, models will be extended towards extreme HBTs, either in SiGe(C) or in III-V materials • RF power devices • For memories models are needed for new memory concepts • FRAM • MRAM • Phase-change memories

  19. Compact Modeling at Circuit Level • Support heterogeneous integration • handle multiple interactions between circuit models, building block models, interconnect, chip, dies and packages • importance of interconnect modeling increases with the stronger contribution to circuit delays and cross talk • interactions between neighboring devices modeled on the basis of the layout including substrate coupling • predictive DC and RF reliability based on device level compact models • device level ESD reliability modeling for future processes • SPICE and behavioral modeling of the failure mechanisms and elementary devices degradation

  20. Summary: ITRS Overview Objective of the ITRS Organization of the ITRS TCAD Challenges ITRS for Compact Modeling

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