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FSSR2 Hybrid PCB Review. January 17, 2013 Matthew Jones. FSSR2 Hybrid PCB Review. Dimensions: 70 mm x 75 mm Layers: 4 Minimum trace width: 0.0762 mm (3 mil) Minimum spacing: 0.0762 mm (3 mil) Via drill: 0.2032 mm (8 mil). FSSR2 Hybrid PCB Review. Board stackup :

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fssr2 hybrid pcb review

FSSR2 Hybrid PCB Review

January 17, 2013

Matthew Jones

fssr2 hybrid pcb review1
FSSR2 Hybrid PCB Review

Dimensions:

70 mm x 75 mm

Layers: 4

Minimum trace width:

0.0762 mm (3 mil)

Minimum spacing:

0.0762 mm (3 mil)

Via drill:

0.2032 mm (8 mil)

fssr2 hybrid pcb review2
FSSR2 Hybrid PCB Review
  • Board stackup:
    • Total thickness: 1.5938 mm (1/16 inch)
    • Copper thickness: 0.0171 mm (1/4 oz/ft2)
    • Equal spacing between layers
  • Layers:
    • TOP: components and secondary signal routing
    • INNER: primary signal routing
    • GROUND: ground plane for signals and power
    • BOTTOM: AVDD and DVDD power planes
  • We assume the manufacturer will adjust layer spacing to maintain target impedance for differential pairs on INNER layer.
fssr2 hybrid pcb review3
FSSR2 Hybrid PCB Review
  • Differential pairs: 100 Ω on INNER layer
    • Trace width: 0.0762 mm, spacing: 0.0870 mm
    • Differential impedance on top layer is not 112 Ω (≠100 Ω)
    • Can’t get 100 Ω on top layer with any sensible trace width
    • Not the primary issue for signal integrity: lots of stubs
    • The board is small, and the data rate is not that high so this shouldn’t be a problem.
    • We could run IBIS to get some idea though…
differential pair modeling
Differential Pair Modeling

One side of the MCLKB signal, running at 100 MHz

  • The tools exist, but I don’t have a lot of confidence in this yet:
  • Default models for all drivers/receivers
  • Cable modeled as a default driver
  • Only looked at one side of MCLKB differential pair so far
    • haven’t looked at differential signals, haven’t looked at crosstalk
  • Haven’t done very many sanity checks yet
fssr2 hybrid pcb review4
FSSR2 Hybrid PCB Review

Mechanical issues:

  • Three holes for mounting screws

(M3 flange button head)

  • Cables enter perpendicular to the board.
  • Connectors:
    • J2: Power (3.3V)
    • J1: Signals (Molex)
    • J3: Bias voltage (MCX)
    • J4: Optional MMCX for charge injection during testing
mounting scheme
Mounting Scheme

Not a great illustration of the mechanics…

Adjacent sensors are mounted on opposite sides of aluminum or carbon fiber plate.

ground plane
Ground Plane
  • There is only one…
power
Power
  • Power requirements are driven by the number of LVDS signals being driven.
  • Estimate: 5 LVDS per chip = 1.5625 Amperes
  • Bring in 3.3V, regulate to 2.5V using LDO regulator:
    • Analog Devices ADP1740ACPZ-2.5
    • 2.0 A maximum output current
    • LFCSP package with exposed ground pad
    • Absolute maximum input voltage is 4V
  • AVDD decoupled from DVDD by ferrite bead
  • Input power connector: Molex 3mm Micro-Fit
  • Input protection provided by a 3.7 V Zener diode
  • Test points provided for AVDD, DVDD, GND, PWR_OK
power planes
Power Planes

With only one power plane there aren’t many other options.

AVDD

DVDD

power to fssr2 chips
Power to FSSR2 Chips

AVDD brought from BOTTOM layer to INNER layer so as to get to the decoupling capacitor.

Decoupling capacitors for AVDD and DVDD

AVDD

GND

DVDD

power2
Power

Molex 0436500226

fssr2 connections
FSSR2 Connections

Hard-wired addresses for each FSSR2 chip (1-5)

fssr2 connections1
FSSR2 Connections

No connections provided to OUT<3..6>. Some signals like OUTCLK could be brought out to test points, but are not on the signal connector. Test points provided for some of the analog signals.

fssr2 connections2
FSSR2 Connections

Internal voltages decoupling

signal routing
Signal Routing

TOP

INNER

Test points for internal analog signals

Bias voltage

Termination resistors

Mostly 100 ohm differential pairs on the inner layer.

gothit logic
GOTHIT Logic

Differential pairs routed to input of 74LVC32 chip, terminated with 100 ohms.

LVDS output driven on cable using SN65LVDS1.

signal connector
Signal Connector

Signal assignment should match what Ryan and Lorenzo suggested…

3M Pak50 Low Profile Plug

0.050” (1.27 mm) spacing.

P50LE-050P1-SML-DA

bias voltage
Bias Voltage

Make sure back side of board is insulated so vias don’t make contact!

Linx CONMCX001-SMD

silkscreen fiducials
Silkscreen/Fiducials

Fiducials for chip and pitch adapter alignment.

1

2

4

8

Binary coded (ie, 7)

pitch adapter
Pitch Adapter
  • A limited number of strips can be wire bonded directly to the readout chip for testing without the pitch adapter.
  • Minimum trace separation for a 1 cm wide pitch adapter is 15 μm.
pitch adapter1
Pitch Adapter

D0 sensor

Bond pads on sensor

Bond pads on pitch adapter

Ratsnest

Bond pads on pitch adapter

FSSR2 chip

PA

pitch adapter2
Pitch Adapter

0.015 mm space between pad and trace

1 mm

Bond pads on FSSR2 chip

photolithography work
Photolithography Work

Line width is 25 μm

(if I recall correctly)

remaining details
Remaining Details
  • It would be interesting to look at some IBIS models of the input clock signals in more detail.
    • No indication that there is a problem, but it would be useful to get more experience using these tools.
  • We could tune trace lengths to match delays on P and N sides of output signals.
  • There is room for test pads for some non-routed signals like OUTCLK.
  • Mechanical example for designing carrier fixture for transportation/wire bonding.