DEC/MEC Onboard Software

1. DEC/MEC Onboard Software A. Mazy Centre Spatial de Liège (B) DEC/MEC OBS (CSL - Liege)

2. Content • Requirements • Design overview • Development status • Tests status • Resources and performances • Documentation • Schedule • Conclusion DEC/MEC OBS (CSL - Liege)

3. DEC/MEC OBS requirements • Mechanisms control (FW, chopper, grating) • Calibration source control (2x) • Receive science data from detectors arrays and BOLC • Control detectors arrays • Forward commands to BOLC • Format science data and HK to send to SPU • Receive commands from DPU • Housekeeping to DPU DEC/MEC OBS (CSL - Liege)

4. Design overview : interfaces DPU BOLC DMC SPUr DECr SPUb DECb Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

5. Design overview DPU DPU Com Sequencer BOLC Com BOLC HK PacketEncoder r DECr Com SPUr DECr PacketEncoder b DECb Com SPUb DECb Mech cntrl CS cntrl Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

6. Design : command handling DPU DPU Com Sequencer BOLC Com BOLC HK PacketEncoder r DECr Com SPUr DECr PacketEncoder b DECb Com SPUb DECb Mech cntrl CS cntrl Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

7. Design : science data handling DPU DPU Com Sequencer BOLC Com BOLC HK PacketEncoder r DECr Com SPUr DECr PacketEncoder b DECb Com SPUb DECb Mech cntrl CS cntrl Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

8. Design : housekeeping DPU DPU Com Sequencer BOLC Com BOLC HK PacketEncoder r DECr Com SPUr DECr PacketEncoder b DECb Com SPUb DECb Mech cntrl CS cntrl Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

9. Design : Miscellaneous • 1355 drivers split in: • 2 interrupts routine to handle read-write • 1 task to handle connection-reconnection • Memory scrubbing: • Cycle through RAM to detect and correct memory errors (EDAC) • Patching: • Automatic procedure to generate patches • Split code in many segments to minimize patches size • Seg_init cannot be split • 1 to 500 TC packets for a simple patch DEC/MEC OBS (CSL - Liege)

10. Design and Coding status DPU DPU Com Sequencer BOLC Com BOLC completed completed completed HK completed PacketEncoder r DECr Com SPUr DECr completed completed PacketEncoder b DECb Com SPUb DECb Mech cntrl CS cntrl completed completed 80% 30% Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

11. Tests and validation • Tests currently performed : • Unstructured tests performed everyday during development of the complete DMC • Some parts (HK, Sequencer, DPU Com) have been used everyday for 3 years. • Validation of the OBS is part of the DMC validation • Test plan : • Issue every command and observe the reaction of the HW (mechanisms, detectors, …) • Test report will be produced (same structure as for AVM) DEC/MEC OBS (CSL - Liege)

12. Tests and validation status DPU DPU Com Sequencer BOLC Com BOLC 90% 90% 80% HK 90% PacketEncoder r DECr Com SPUr DECr 90% 80% PacketEncoder b DECb Com SPUb DECb Mech cntrl CS cntrl 90% 80% 50% 20% Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

13. Interface Status Issue 1.1 stable Issue 3.5 stable DPU BOLC DMC Issue 3.4 stable Internal stable SPUr DECr Issue 3.4 stable Internal stable SPUb DECb Internal ~stable Internal partially defined Mechanisms Calib src DEC/MEC OBS (CSL - Liege)

14. Resources and performances Memory CPU load : Max 60% DEC/MEC OBS (CSL - Liege)

15. Documentation produced • SSD issue 1.0 • ICD DMC-DPU issue 3.5 • ICD DMC-SPU issue 3.4 • SUM issue 2.5 • HSIA draft DEC/MEC OBS (CSL - Liege)

16. Schedule • Finalize patching : few days • Finalize Mechanisms control : 1 week • Finalize Calibrations source control : 1 week • Tests and validation : 2 weeks • Schedule highly related to extension boards and mechanisms availability/schedule. DEC/MEC OBS (CSL - Liege)

17. Progress Made since IBDR and Conclusions • Design and code almost complete (95%) • SSD updated (issue 1.0) • Stable interfaces • Tests almost complete (90%) • Formal validation still to be done DEC/MEC OBS (CSL - Liege)