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Virtual Platforms for Memory Controller Design Space Exploration. Matthias Jung , Christian Weis, Norbert Wehn University of Kaiserslautern, Germany. Standard Memory System. Bandwidth Requirements. Memory Wall. CORE. n s. Power hungry I/O transceivers. 16B. m s. m s. L1 private

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virtual platforms for memory controller design space exploration

Virtual Platforms for Memory Controller Design Space Exploration

  • Matthias Jung, Christian Weis, Norbert Wehn
  • University of Kaiserslautern, Germany
standard memory system
Standard Memory System

Bandwidth Requirements

Memory Wall

CORE

ns

Power hungry I/O transceivers

16B

ms

ms

L1 private

cache

64KB

L2 private cache

256KB

Memory Controller: 3 Channels

512B

64B

L3 shared cache

8-12MB

.

Pin limitation due to package

SRAM

DRAM

HDD/SSD

3d stacked wide i o dram
3D Stacked Wide I/O DRAM
  • Stacked DRAM dies
  • TSV connections
  • Multiple Channels

Higher available bandwidth

3D stacked DRAM

1 or 2

Channel

DDR3

Memory

controller

bottleneck

MPSoC

Increasing bandwidth demand

 New generation of Memory Controllers is required

design space exploration with virtual platforms
Design Space Exploration with Virtual Platforms
  • Huge design space of 3D-DRAM controller
  • Flexible and cycle approx. models are needed for fast investigation
  • RTL simulation is too slow for system level analysis
  •  TLM based virtual platforms with Synopsys Platform Architect Speedup of TLM models up to 377xcompared to CA1 Simulating in seconds instead of hours

1 M. Jung, et al. TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, in Proc. HiPEAC Conference 2013, Berlin.

special tlm dram protocol 1
Special TLM DRAM Protocol1
  • Application specific phases with DECLARE_EXTENDED_PHASE()
  • Phases derived from DRAM commands (Jedec Wide I/O Standard)
  • DRAM commands: ACT, PRE, RD, WR, REFA …

Example:

1 M. Jung, et al. TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, HiPEAC, 2013, Berlin.

experiments and results
Experiments and Results
  • TLM model was compared with cycle accurate SystemC implementation
  • Tested with Mediabench and CHStone Benchmark traces

42s

1h 41m

Speedup up to two magnitudes!

power modeling of 3d dram with tlm2 0 2
Power Modeling of 3D-DRAM with TLM2.02

Two parts of power consumption:

  • Background Power
  • Command Power
  •  DRAM Power states accounted with TLM phases

I

t

ACT

WR

PRE

ACT

RD

WR

PRE

2 M. Jung et al. Power Modelling of 3D-Stacked Memories with TLM2.0, SNUG 2013, Munich

results power simulation
Results (Power Simulation)
  • TLM model was compared with a cycle accurate SystemC implementation and the standalone power simulator DRAMPower3
  • Tested with Mediabench and CHStone Benchmark traces

Deviation max 5% to reference

models

3www.drampower.info

current work thermal simulation
Current Work: Thermal Simulation
  • Co-simulation with 3D-ICE Simulator3
  • Traces will be generated from GEM54
  • Closed Loop Control

3 http://esl.epfl.ch/3d-ice.html 4 http://www.gem5.org/

conclusion
Conclusion
  • 3D stacked DRAMs are the future technology
  • Virtual platform for DSE of new multi-channel Wide I/O DRAM controllers are mandatory
  • DRAM specific TLM protocol was introduced(can be used for any kind of DRAM)
  • Precise Power model presented
  • Early checkpoint for SW implementations
  • Current and Future Work: Advanced scheduling and arbitration algorithms
slide11

Thank you!

Visit my Poster!http://www.uni-kl.de/3d-dram