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Reliability Analysis of the Aeroflex ViaLink™ FPGA. MAPLD International Conference September 8, 2005 Session D: Reliability Ronald Lake Aeroflex Colorado Springs www.aeroflex.com/radhardFPGA. Agenda. Background Aeroflex begins QML-Q / QML-V Qualification of RadHard Eclipse FPGA

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Reliability analysis of the aeroflex vialink fpga
Reliability Analysis of the Aeroflex ViaLink™ FPGA

MAPLD International Conference

September 8, 2005

Session D: Reliability

Ronald Lake

Aeroflex Colorado Springs

www.aeroflex.com/radhardFPGA

MAPLD2005 / Submission 222


Agenda
Agenda

  • Background

    • Aeroflex begins QML-Q / QML-V Qualification of RadHard Eclipse FPGA

    • Original approach followed MIL-PRF-38535 standards

    • Approach outlined in previously published papers

    • Then the world changed (Industry Tiger Team, Aerospace Corp., NASA GSFC, etc.)

  • New Approach

    • November 2004: Aeroflex received “Aerospace Requirements for FPGAs in Space”

    • Aeroflex adopts enhanced MIL-PRF-38535 QML Qualification with Aerospace Corporation guidelines

      • Un-programmed burn-in

      • Operating life test (HTOL / LTOL)

  • Current Status

    • Aeroflex completes QML-Q / QML-V qualification: August 2005

    • Standard Microcircuit Drawing (SMD) #:5962R04229

    • Aeroflex announces QML results: September 2005 (MAPLD)

    • Aeroflex ships first Rad-Assured QML materials: September 2005

MAPLD2005 / Submission 222


Qml qualification compliance matrix
QML Qualification Compliance Matrix

Aeroflex vs. Aerospace Corp. Guidance

MAPLD2005 / Submission 222


Aerospace evaluation

Sample Type/Description

Task

Completion

  • Programmed

  • Un-Programmed

  • Elemental

  • Structural

3Q2005

  • 1, 3 and 5 pulse programmed ViaLinks (bi-directional)

  • Uni-Directionally Programmed ViaLink

  • Unprogrammed ViaLink

  • Elemental

  • Structural

4Q2005

Aerospace Evaluation

  • Structural Evaluation

    • Using focused ion beam techniques

    • Output – 3 dimension model (colorized)

  • Follow-on evaluations

    • Effect on adjacent ViaLinks

    • Lot to Lot variation

    • Via Links vs Programming

    • Spatial Wafer Evaluation (center to edge)

    • Lot to Lot variations

    • Failed ViaLink (if possible)

MAPLD2005 / Submission 222


Un programmed vialink cross section
Un-programmed ViaLink Cross Section

Figure removed until

Proprietary issues are resolve.

This was a late arriving paper

and I apologize for this, I was

too nice and will fix that for

MAPLD 2006. -- rk

MAPLD2005 / Submission 222


Reliability design for vialink operating life
Reliability Design for ViaLink Operating Life

  • Goal: Create worst case design for ViaLink stress

    • Adhere to NASA OLD guidelines for reliability test vehicles for fuse based FPGAs

  • Design

    • Use all FPGA logic, memory and I/O resources

    • Use all wiring types, with associated ViaLinks

    • Force high fan-out structures for flip flops and logic

    • Maximize current density through ViaLinks

    • Manually fix placement to force use of long wires and worst case ViaLinks

    • Use dedicated and global clocks for synchronous logic

    • Synchronize reset to insure initialization conditions

    • Create long combinatorial and synchronous chains for AC delay measurements

MAPLD2005 / Submission 222


Life test environment for radhard eclipse
Life Test Environment for RadHard Eclipse

  • Goal: Subject RadHard Eclipse to real world environment during life test to stress ViaLinks

  • Life test conditions

    • Do not de-couple or terminate I/O signals

    • Allow voltage spikes on inputs

    • Allow noise on I/O and within wiring array of ViaLinks

    • Evaluate multiple power sequencing conditions

    • Use extended times in stress chambers

    • Closely monitor power supplies

MAPLD2005 / Submission 222


Test environment for characterization
Test Environment for Characterization

  • Goal: Create repeatable and accurate test environment for measurement of RadHard Eclipse ViaLink characteristics

  • Test Conditions

    • Use Teradyne Tiger tester for accurate measurements of quiescent current and propagation delay

    • Test all temperature conditions: -55ºC, 25ºC and 125ºC

    • Test all voltage conditions: 2.3V core and 3.0V I/O; 2.5V core and 3.3V I/O; 2.7V core and 3.6V I/O

    • Use control units to verify test environment does not change between stress read points

    • Review all test results prior to next stress, comparing worst case deltas to means

MAPLD2005 / Submission 222


Un programmed burn in
Un-programmed burn-in

  • Applied to 100% of un-programmed units passing manufacturing stress

  • Standard step in Aeroflex QML manufacturing flow

  • 240 hrs of 125°C burn-in at maximum operating conditions (Vcc=2.7V, Vccio=3.6V)

  • FPGAs dynamically stimulated during burn-in

  • After burn-in devices tested for quiescent current (Icc, Iccio) and un-programmed electrical test (3 temperature, min/typ/max voltage)

  • Percent defective allowable (PDA) <5%

MAPLD2005 / Submission 222


Operating life ac deltas
Operating Life AC Deltas

  • LTOL: 77 test units + 3 control

    • No ViaLink failures at 1000 Hrs stress

    • <3% change in propagation delay

  • HTOL: 77 test units + 3 control

    • No ViaLink failures at 1000 Hrs stress

    • <10% change in propagation delay

  • Delay deltas calculated for all voltage & temperature combinations

MAPLD2005 / Submission 222


Co60 ac deltas
Co60 AC Deltas

  • Delta’s calculated at room temperature for all voltage combinations

  • <5% change in delay at 100 krad(Si)

  • <15% change in delay at 300 krad(Si)

  • Irradiated at 1 rad(Si)/sec

  • Propagation delays stay within simulation limits

MAPLD2005 / Submission 222


Radiation testing
Radiation Testing

Single

Event Effects

Total Ionizing Dose

Dose Rate

MAPLD2005 / Submission 222


Timing characterization
Timing Characterization

QuickLogic Timing Release Flow

  • Current Status

    • Aeroflex speed grade -5 primitive library provides >10% guard band vs. silicon for combinatorial and most synchronous delays

    • Margins maintained for material after TID of 300krads (Si)

    • Some exceptions exist due to Aeroflex removal of charge pump on FPGA

    • Delay library undergoing updates for 4Q2005 release

Oscillator Design

(34 types)

Initial Data

Collection

Re-Simulate Oscillator

Designs

Silicon

Vs Simulation

Spde Release

Timing Generation

  • Pre Release Data

  • Aeroflex

  • Aeroflex

  • QuickLogic

  • Aeroflex

  • Aeroflex

  • QuickLogic

Verification Loop

MAPLD2005 / Submission 222


Summary
Summary

  • Aeroflex Colorado Springs has embraced the Aerospace Corporation’s guidelines to enhance the QML qualification flow

  • Burn-in analysis demonstrates <3 % defective after 3 temperature testing (QML lot acceptance PDA<5%)

  • Worst case conditions used for ViaLink™ operating life test

    • LTOL delay analysis demonstrates <3 % change in propagation delay after 1000 Hrs of stress

    • HTOL delay analysis demonstrates <10% change in propagation delay after 1000 Hrs of stress

  • TID delay analysis demonstrates <5% change in propagation delay at 100krad and <12% change at 300krad

  • ViaLink structural and elemental analysis underway with Aerospace Corporation

  • RadHard Eclipse FPGA qualified as Rad-Assured QML Q/V

MAPLD2005 / Submission 222


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