1 / 9

Test Fixture Template

Test Fixture Template. module testfixture ; // data type declaration // instantiate modules under test // Applying stimulus // Display results endmodule. Test Fixture - Data Type Declaration. module testfixture ; // data type declaration

ull
Download Presentation

Test Fixture Template

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Test Fixture Template module testfixture ; // data type declaration // instantiate modules under test // Applying stimulus // Display results endmodule

  2. Test Fixture - Data Type Declaration module testfixture ; // data type declaration reg a, b, sel ; // the inputs of Device Under Test // instantiate modules under test // Applying stimulus // Display results endmodule

  3. Test Fixture - Instantiate module testfixture ; // data type declaration reg a, b, sel ; // the inputs of Device Under Test // instantiate modules under test mux2_1 u1 (out, a, b, sel) ; // Applying stimulus // Display results endmodule

  4. Test Fixture - Stimulus module testfixture ; // data type declaration reg a, b, sel ; // the inputs of Device Under Test // instantiate modules under test mux2_1 u1 (out, a, b, sel) ; // Applying stimulus using an initial block initial begin a=0 ; b=1 ; sel=0 ; #5 b=0 ; #5 b=1 ; sel=1 ; end // Display results endmodule

  5. Display results //Display results initial begin $display(" time out a b sel"); $monitor($time, " %b %b %b %b", out,a,b,sel) ; end // Generate waveform initial begin $shm_open("mux.shm"); $shm_probe("AS"); end

  6. Lab 1: Verilog for Combinational Ckts • Set up workstation environment • .cshrc • Cadence on-line manual • openbook • Verilog-XL User Guide • Verilog-XL Reference • Verilog-XL Tutorial • Two simple examples • 2-to-1 multiplexor (structural) • 3-to-8 decoder • Verilog simulation and simwave

  7. 7-segment decoder • input [3:0] in; • output a,b,c,d,e,f ; • Active low • RTL description • always block • Always @ (in) • a test fixture • print out waveform

  8. 4-bit magnitude comparator • input [3:0] a, b ; • input agb, alb, aeb ; • output agbo, albo, aebo ; • RTL description • Check inputs with high priority first • quiz

  9. The truth table

More Related