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第 3 章 组合逻辑电路的分析和设计 Combinational Logic Circuit

第 3 章 组合逻辑电路的分析和设计 Combinational Logic Circuit. 本章主要内容. 1.MSI 的应用 2. 组合逻辑电路的分析方法 3. 组合逻辑电路的设计方法. Sec3.1 Summarize. Logic circuit Categorize 1.Combination Logic circuit 2.Sequence Logic Circuit 3.State -Machine. The concept of combinational Logic circuit. Xi1 Xi2 Xin. Combina

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第 3 章 组合逻辑电路的分析和设计 Combinational Logic Circuit

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  1. 第3章 组合逻辑电路的分析和设计 Combinational Logic Circuit

  2. 本章主要内容 • 1.MSI的应用 • 2.组合逻辑电路的分析方法 • 3.组合逻辑电路的设计方法

  3. Sec3.1 Summarize • Logic circuit Categorize • 1.Combination Logic circuit • 2.Sequence Logic Circuit • 3.State -Machine

  4. The concept of combinational Logic circuit Xi1 Xi2 Xin Combina -tional Logic Circuit YO1 YO2 YOm

  5. Features of Combination circuits • ⑴.组和逻辑电路可以 是多输入多输出逻辑电路； • ⑵.输入变量只有“0”、“1”两种状态，因此n个输入变量有2n种输入组和状态； • .

  6. Sec3.2 Combinational Logic Circuit Analysis Method • 1.The Object of Analysis: • Finding the function of the Logic circuit • 2. Analysis step: • ⑴.根据逻辑图，写出输出端逻辑关系表达式； • ⑵.化简此逻辑函数成最简表达式； • ⑶.列出真值表，把各组输入状态下的输出状态求出； • ⑷.写出逻辑真值表，得到逻辑功能的说明。

  7. The Example of Analysis Method

  8. Combination Logic analysis methodsExample-1 A B C P1 F P2 P3

  9. Half adder with Carry bitExample-2 P2 A B S=A⊕B A S C P1 S C P3 B

  10. ∑ A ∑ B Co Sum Input bits Output bits Carry Half Adder S=A⊕B ⊕ Sum carry C=AB

  11. Sec3.3 Design Method of combination Logic circuit • 1.Design Step： • ⑴.建立描述逻辑问题的真值表 • ①.分析题目所给的条件； • ②.找出问题的条件与目的及因果关系； • ③.确定输入、输出变量； • ④.列出真值表； • ⑵.由真值表写出逻辑函数表达式；(用最小项机制和的形式。) • ⑶．对输出逻辑函数进行化简。 • ⑷．画出逻辑电路图。

  12. Sum C0ut Full Adder A B Cin 2.Full Adder (carry-less Output) Output un-carry Full Adder Ai Bi Ai⊕ Bi⊕ C in Ci-1

  13. 3.Full Adder circuit (with carry Output)--1 Ai⊕Bi⊕Ci-1 ( Ai⊕Bi)Ci-1+AiBi

  14. Full Adder (other type)--2 Ai⊕Bi Half Adder Half Adder ( Ai⊕Bi)⊕Ci-1 ( Ai⊕Bi)Ci-1+AiBi ( Ai⊕Bi)Ci-1

  15. Full Adder--3 D.D.P.219 Ai Bi Cin ( Ai⊕Bi) ⊕Cin AiBi+AiCin+BiCin

  16. 4. Full Adder Application A 4-bit parallel adder A2 B2 A1 B1 A4 B4 A3 B3 C0 A B Ci Co S A B Ci Co S A B Ci Co S A B Ci Co S C4 S1 S2 S4 S3 LSB MSB

  17. 5.The first two stages of a carry- look ahead adder A1 B1 A0 B0 g1 p1 g0 p0 C0 S1 S0 VHDL.p.249

  18. 4-bits Full Adder with fast carry 74xx83;74C283,4008

  19. Sec.3.3 Binary 1’s complement subtraction: • To subtract using 1’s complement: • To take the 1’s complement of the subtrahend (bottom number); • Add the 1’s complement to the minuend (top number); • Overflow indicates that the answer is positive. Add the • Overflow to the least significant bit. This operation is called end – around carry (EAC). • If there is no overflow then the answer is negative, take the 1’s complement of original sum to obtain the true magnitude of the answer. D.E. p.216

  20. 1. 1’s complement Adder/Subtractor circuit 0=add 1=subtract 7483 C0 B4 A4 B3 A3 B2 A2 B1 A1 C4 ∑4 ∑3 ∑2 ∑1 D.E.p.219

  21. 1’s complement Adder/ Subtractor circuit C0 C4 7483 0=add 1=subtract D.E.p.219

  22. 2. The 1’s complement method for subtraction using Adder/ Subtractor • 1. Leave the number B1~4 unaltered for an addition problem, but take the 1’s complement of the subtrahend for a subtraction problem. • When Control = 1 : an exclusive inverts data( 1’s complement); • for subtraction; • When Control = 0: for addition; • If the problem. is subtraction and if there is overflow(C4= 1), perform an EOC. The output of AND gate No.1 can be fed directly into C0. • If the problem. is subtraction and if there is overflow(C4 = 0), indicate the answer is negative and take 1’s complement of the result to obtain the true magnitude of the answer. 1. 2. 3.

  23. Full adder(1’s complement adder/subtractor) D.E.p.219~p.221 0=Add 1=Subtract A4 A3 A2 A1 C0 B4 A4 B3 A3 B2 A2 B1 A1 ∑4 ∑3 ∑2 ∑1 c4 c4 +5v ∑4 ∑3 ∑2 ∑1

  24. Sec.3.4 Binary 2’s complement of subtractor • Methods: • To form the 2’s complement of a number, first take the 1’s complement and then add 1. • A shorter method is to start at the least significant bit , and moving to the left , leave each bit the same until the first 1is passed. Then change each bit thereafter. Digital-2 p.108

  25. 1. To subtract using the 2’s complement • Take the 2’s complement of the subtrahend (bottom number ), • Add it to the minuend (top number). • Overflow indicates that the answer is positive. Ignore the overflow (no end-around carry ). • No overflow indicates that the answer is negative. Take the 2’s complement of the original sum to obtain the true magnitude of the answer. D. E. p.225//Digital-2.p.109

  26. 2. 1 Bit comparator ( Equal Output ) D.D.P.175 F=A⊕B=A⊙B

  27. 2. 4 Bit comparator ( Equal Outbut ) D.E.P.175 74AC11521 8-bit identity 74ACT520 8-bit identity 74FCT521 8-bit identity

  28. C0 A4 B4 A3 B3 A2 B2 A1 B1 C4

  29. 1- bit Magnitude comparator A B A B

  30. A four – bit comparator circuit VHDL.D.p.305 i2 i1 i0

  31. 74LS85 4-bit magnitude comparator D.E.p.177 1 0 1 0 0 1 1 1 10 9 A0 B0 A1 B1 A2 B2 A3 B3 IA<B IA=B IA>B 12 QA<B QA=B QA>B 7 11 1 0 0 13 14 6 15 1 5 2 3 +5V A= 1011 B =1100 4 CC14585 Book:p.170

  32. 4-bit comparator-1 D.D.p.421 74X86 DIFF

  33. Sec.3.5 Multiplexer • 1.Defined: • A Multiplexer is a digital switch-----it connects data from one of n sources to its output.

  34. (a) Graphical symbol (b) Truth table s W0 f W1 2. Multiplexers s f Input W0 w1 0 1 W0 w1 0 1

  35. (d)circuit with transmission gates W0 F S W1 (c)sum-of-products circuit Multiplexer Digital signal Analog signal

  36. 3. A 4-to-1 multiplexer D0 S0 S1 D1 D0 D2 D1 00 01 10 11 F D3 D3 S0 S1 D3

  37. 4. Multiplexer applications E’

  38. 74X157 15 1 2 3 5 6 11 10 14 13 G S 1A 1Y 1B 2A 2Y 2B 3A 3Y 3B 4A 4Y 4B 4 7 9 12 74X157 2-Input, 4-bit multiplexer D.D.P.400

  39. Da0 Da1 Da2 Da Ea’ Db0 Db1 Db2Db3Eb’ Y00 E’ + Y11 4-input, 2-bit multiplexer: 74LS153

  40. 1 D0 D1 D2 D3 E’ S1 S0 y E’ A1 A0 5. Multiplexer as a function generator 0

  41. Sec3.6 Decoder: • 1.Defined of Decoder • Decoder---The circuit which select a unique • output line for each of a set of • binary address , are known as • decoder.

  42. Decoder Categorize & Applications • 1.Binary Decoder(74LS138). • 2.BCD Decoder(二 - 十进制). • 3.Display Decoder(7 Segment Display). • 4.Applications.

  43. 2. A 2-to-4 decoder En y0 A y0 y1 B y1 y2 y2 y3 En y3 A B

  44. 010 011 001 100 101 110 111 000 Y’1 Y’2 Y’3 Y’4 Y’6 Y’0 Y’5 Y’7 1 2 3 4 5 6 7 8 B C A A’ B’ C’ E A B C S1 S3 3. 3-8 Decoder S2

  45. 74LS138 Decoder

  46. ⑴. 16 bits addresses decoder

  47. 2. Extended 64 I/O ports address

  48. 3. Data Demultiplexer

  49. 4. Decoder implement function generator:

  50. D’ S A A’ B B’ C C’ D Output line 0 Y’0 =D’C’B’A’ 1 Y’1 =D’C’B’A : : : =DC’B’A’ 8 Y’8 9 Y’9 =DC’B’A

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